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GM5120-H Schematic ( PDF Datasheet ) - ETC

Teilenummer GM5120-H
Beschreibung (GM5110 / GM5120) XGA/SXGA LCD Controller
Hersteller ETC
Logo ETC Logo 




Gesamt 30 Seiten
GM5120-H Datasheet, Funktion
www.DataSheet4U.com
Genesis Microchip Publication
PRELIMINARY DATA SHEET
gm5110/gm5110-H
gm5120/gm5120-H
XGA/SXGA LCD Controller
*** Genesis Microchip Confidential ***
NOTE: Sections in this data sheet that mention HDCP apply only to the HDCP-enabled chip
versions (gm5110-H and gm5120-H). All other sections apply to all chip versions (gm5110,
gm5110-H, gm5120, and gm5120-H).
Publication number: C5110-DAT-01C
Publication date: June 2002
Genesis Microchip Inc.
2150 Gold Street, Alviso, P.O. Box 2150, CA USA 95002 Tel: (408) 262-6599 Fax: (408) 262-6365
165 Commerce Valley Dr. West, Thornhill, ON Canada L3T 7V8 Tel: (905) 889-5400 Fax: (905) 889-5422
1096, 12thA Main, Hal II Stage, Indira Nagar, Bangalore-560 008, India, Tel: (91)-80-526-3878, Fax: (91)-80-529-6245
4F, No. 24, Ln 123, Sec 6, Min-Chuan E. Rd., Taipei, Taiwan, ROC Tel: 886-2-2791-0118 Fax: 886-2-2791-0196
143-37 Hyundai Tower, #902, Samsung-dong, Kangnam-gu, Seoul, Korea 135-090 Tel 82-2-553-5693 Fax 82-2-552-4942
Rm2614-2618 Shenzhen Office Tower, 6007 Shennan Blvd, 518040, Shenzhen, Guandong, P.R.C., Tel (0755)386-0101, Fax (0755)386-7874
2-9-5 Higashigotanda, Shinagawa-ku, Tokyo, 141-0022, Japan, Tel 81-3-5798-2758, Fax 81-3-5798-2759
www.genesis-microchip.com / [email protected]






GM5120-H Datasheet, Funktion
*** Genesis Microchip Confidential ***
gm5110/20 Preliminary Data Sheet
List Of Tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Analog Input Port...................................................................................................4
DVI Input Port .......................................................................................................5
RCLK PLL Pins .....................................................................................................5
Analog HSYNC/VSYNC Inputs............................................................................6
System Interface and GPIO Signals.......................................................................6
Display Output Port ...............................................................................................7
Parallel ROM Interface Port ..................................................................................8
Reserved Pins.........................................................................................................8
Power Pins for ADC Sampling Clock DDS ..........................................................9
Power Pins for Display Clock DDS.......................................................................9
I/O Power and Ground Pins ...................................................................................9
Core Power and Ground Pins.................................................................................9
TCLK Specification .............................................................................................14
Pin Connection for RGB Input with HSYNC/VSYNC .......................................17
ADC Characteristics ............................................................................................18
DVI Receiver Characteristics ..............................................................................20
gm5110/20 GPIOs and Alternate Functions ........................................................35
Bootstrap Signals .................................................................................................36
Instruction Byte Map ...........................................................................................37
Absolute Maximum Ratings ................................................................................40
DC Characteristics ...............................................................................................41
Maximum Speed of Operation.............................................................................42
Display Timing and DCLK Adjustments ............................................................42
2-Wire Host Interface Port Timing ......................................................................42
June 2002
v C5110-DAT-01C

6 Page









GM5120-H pdf, datenblatt
*** Genesis Microchip Confidential ***
gm5110/20 Preliminary Data Sheet
Pin Name
AVDD_IMB
REXT
AGND_IMB
VDD_RX2_2.5
GND_RX2
AGND_RX2
RX2+
RX2-
AVDD_RX2
VDD_RX1_2.5
GND_RX1
AGND_RX1
RX1+
RX1-
AVDD_RX1
VDD_RX0_2.5
GND_RX0
AGND_RX0
RX0+
RX0-
AVDD_RX0
RXC+
RXC-
AVDD_RXC
AGND_RXC
GND_RXPLL
VDD_RXPLL_2.5
CLKOUT
Pin Name
AVDD_RPLL
AVSS_RPLL
TCLK
XTAL
VDD_RPLL
VSS_RPLL
Table 2. DVI Input Port
No I/O Description
173 AP
174 AI
175 AG
176 P
177 G
178 AG
179 AI
180 AI
181 AP
182 P
183 G
184 AG
185 AI
186 AI
187 AP
188 P
189 G
190 AG
191 AI
192 AI
193 AP
194 AI
195 AI
196 AP
197 AG
198 G
199 AP
201 AO
Analog VDD (3.3V) for internal biasing circuits.
Must be bypassed with decoupling capacitors (as close as possible to the pin).
External reference resistor.
An external 1Kohm (1%) resistor should be connected from this pin to AVDD_IMB pin.
Analog GND for internal biasing circuits.
Must be connected directly to the ground plane.
VDD (2.5V) for DVI input pair 2 logic circuits. Must be bypassed with decoupling capacitor to
GND_RX2 pin (as close as possible to the pin).
GND for DVI input pair 2 logic circuits.
Must be connected directly to the ground plane.
Analog GND for DVI input pair 2 input buffer.
Must be connected directly to the analog ground plane.
DVI input pair 2
DVI input pair 2
Analog VDD (3.3V) for DVI input pair 2 input buffer. Must be bypassed with decoupling
capacitor to AGND_RX2 pin (as close as possible to the pin).
VDD (2.5V) for DVI input pair 1 logic circuits. Must be bypassed with decoupling capacitor to
GND_RX1 pin (as close as possible to the pin).
GND for DVI input pair 1 input buffer.
Must be connected directly to the analog ground plane.
Analog GND for DVI input pair 1 input buffer.
Must be connected directly to the analog ground plane.
DVI input pair 1
DVI input pair 1
Analog VDD (3.3V) for DVI input pair 1 input buffer. Must be bypassed with decoupling
capacitor to AGND_RX1 pin (as close as possible to the pin).
VDD (2.5V) for DVI input pair 0 logic circuits. Must be bypassed with decoupling capacitor to
GND_RX0 pin (as close as possible to the pin).
GND for DVI input pair 0 logic circuits.
Must be connected directly to the ground plane.
Analog GND for DVI input pair 0 input buffer.
Must be connected directly to the analog ground plane.
DVI input pair 0
DVI input pair 0
Analog VDD (3.3V) for DVI input pair 0 input buffer. Must be bypassed with decoupling
capacitor to AGND_RX0 pin (as close as possible to the pin).
DVI input clock pair
DVI input clock pair
Analog VDD (3.3V) for DVI input clock pair input buffer. Must be bypassed with 100pF
capacitor to AGND_RXC pin (as close as possible to the pin).
Analog GND for DVI input clock pair input buffer.
Must be connected directly to the analog ground plane.
Digital GND for the DVI receiver internal PLL.
Must be connected directly to the system ground plane.
Analog VDD (2.5V) for the DVI receiver internal PLL. Must be bypassed with a decoupling
capacitor to AGND_RXPLL pin (as close as possible to the pin).
For test purposes only. Do not connect.
Table 3. RCLK PLL Pins
No I/O Description
150 AP
149 AG
152 AI
151 AO
148 P
147 G
Analog power for the Reference DDS PLL. Connect to 3.3V supply. Must be bypassed with a
0.1uF capacitor to pin AVSS_RPLL (as close to the pin as possible).
Analog ground for the Reference DDS PLL.
Must be directly connected to the analog system ground plane.
Reference clock (TCLK) from the 14.3MHz crystal oscillator, or from single-ended
CMOS/TTL clock oscillator (refer to Figure 7). This is a 5V-tolerant input.
Crystal oscillator output.
Digital power for RCLK PLL. Connect to 3.3V supply.
Digital ground for RCLK PLL.
June 2002
5 C5110-DAT-01C

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