|
|
PDF 74LVQ161 Data sheet ( Hoja de datos )
| Número de pieza | 74LVQ161 | |
| Descripción | SYNCHRONOUS PRESETTABLE 4-BIT COUNTER | |
| Fabricantes | STMicroelectronics | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de 74LVQ161 (archivo pdf) en la parte inferior de esta página. Total 14 Páginas | ||
|
No Preview Available !
www.DataSheet4U.com
74LVQ161
SYNCHRONOUS PRESETTABLE 4-BIT COUNTER
s HIGH SPEED:
fMAX = 180 MHz (TYP.) at VCC = 3.3 V
s COMPATIBLE WITH TTL OUTPUTS
s LOW POWER DISSIPATION:
ICC = 4 µA (MAX.) at TA=25°C
s LOW NOISE:
VOLP = 0.3V (TYP.) at VCC = 3.3V
s 75Ω TRANSMISSION LINE DRIVING
CAPABILITY
s SYMMETRICAL OUTPUT IMPEDANCE:
|IOH| = IOL = 12mA (MIN) at VCC = 3.0 V
s PCI BUS LEVELS GUARANTEED AT 24 mA
s BALANCED PROPAGATION DELAYS:
tPLH ≅ tPHL
s OPERATING VOLTAGE RANGE:
VCC(OPR) = 2V to 3.6V (1.2V Data Retention)
s PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 161
s IMPROVED LATCH-UP IMMUNITY
DESCRIPTION
The 74LVQ161 is a low voltage CMOS
SYNCHRONOUS PRESETTABLE COUNTER
fabricated with sub-micron silicon gate and
double-layer metal wiring C2MOS technology. It is
ideal for low power and low noise 3.3V
applications. It is a 4 bit binary counter with
Asynchronous Clear.
The circuit have four fundamental modes of
operation, in order of preference: synchronous
SOP
TSSOP
Table 1: Order Codes
PACKAGE
SOP
TSSOP
T&R
74LVQ161MTR
74LVQ161TTR
reset, parallel load, count-up and hold. Four
control inputs, Master Reset (CLEAR), Parallel
Enable Input (PE) and Count Enable Carry Input
(TE), determine the mode of operation as shown
in the Truth Table. A LOW signal on CLEAR
overrides counting and parallel loading and sets
all outputs on LOW state. A LOW signal on LOAD
overrides counting and allows information on
Parallel Data Qn inputs to be loaded into the
flip-flops on the next rising edge of CLOCK. With
LOAD and CLEAR, PE and TE permit counting
when both are high. Conversely, a LOW signal on
either PE and TE inhibits counting. All inputs and
outputs are equipped with protection circuits
against static discharge, giving them 2KV ESD
immunity and transient excess voltage.
Figure 1: Pin Connection And IEC Logic Symbols
July 2004
Rev. 2
1/14
1 page  
74LVQ161
Table 8: AC Electrical Characteristics (CL = 50 pF, RL = 500 Ω, Input tr = tf = 3ns)
Test Condition
Symbol
Parameter
VCC
(V)
tPLH tPHL Propagation Delay
Time CK to Q
tPLH tPHL Propagation Delay
Time CK to CARRY
OUT
tPLH tPHL Propagation Delay
Time TE to CARRY
OUT
tPHL Propagation Delay
Time CLR to Q
tPHL
tW(L)
Propagation Delay
Time CLR to
CARRY OUT
CLR Pulse Width,
LOW (LOAD)
tW
ts
th
ts
th
ts
th
tREM
CLOCK Pulse
Width, HIGH or
LOW
Setup Time HIGH
or LOW
(INPUT to CLOCK)
Hold Time HIGH or
LOW
(INPUT to CLOCK)
Setup Time HIGH
or LOW (LOAD to
CLOCK)
Hold Time HIGH or
LOW (LOAD to
CLOCK)
Setup Time HIGH
or LOW (PE or TE
to CLOCK)
Hold Time HIGH or
LOW (PE or TE
to CLOCK)
Recovery Time
CLR to CK
fMAX Maximum Clock
Frequency
tOSLH
tOSHL
Output To Output
Skew Time
(note1, 2)
2.7
3.3(*)
2.7
3.3(*)
2.7
3.3(*)
2.7
3.3(*)
2.7
3.3(*)
2.7
3.3(*)
2.7
3.3(*)
2.7
3.3(*)
2.7
3.3(*)
2.7
3.3(*)
2.7
3.3(*)
2.7
3.3(*)
2.7
3.3(*)
2.7
3.3(*)
2.7
3.3(*)
2.7
3.3(*)
Value
TA = 25°C
-40 to 85°C -55 to 125°C Unit
Min.
Typ.
8.0
6.8
9.1
7.5
Max.
13.0
9.5
14.0
10.5
Min.
Max.
15.0
11.0
16.0
12.0
Min. Max.
17.0
12.5
18.5
14.0
ns
ns
5.6 10.0 11.5 13.0
4.7 8.0
ns
9.5 10.5
8.0 12.0
6.1 9.5
8.0 14.0
6.7 10.5
15.0
11.0
16.0
12.0
17.0
12.5
18.5
14.0
ns
ns
4.0 1.9 4.0 4.0
3.0 1.9 3.0 3.0
4.0 1.9 4.0 4.0
3.0 1.9 3.0 3.0
ns
ns
5.0 2.5 5.0 5.0
4.0 2.1 4.0 4.0
ns
1 -1.3
1
1
0.5 -1.0 0.5 0.5
ns
3.0 1.5 3.0 3.0
2.5 1.2 2.5 2.5
ns
1 -0.6
1
1
0.5 -0.5 0.5 0.5
ns
7.0 3.4 7.0 7.0
6.0 3.0 6.0 6.0
ns
0 -2.6
0 -2.2
0
0
0
ns
0
1 -0.8
1
1
0.5 -0.6 0.5 0.5
ns
100 150
120 180
80
100
60
MHz
80
0.5 1.0 1.0 1.0
0.5 1.0 1.0 1.0 ns
1) Skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs of the same device switch-
ing in the same direction, either HIGH or LOW (tOSLH = |tPLHm - tPLHn|, tOSHL = |tPHLm - tPHLn|)
2) Parameter guaranteed by design
(*) Voltage range is 3.3V ± 0.3V
5/14
5 Page 
DIM.
A
C
D
N
T
Ao
Bo
Ko
Po
P
74LVQ161
Tape & Reel SO-16 MECHANICAL DATA
MIN.
12.8
20.2
60
6.45
10.3
2.1
3.9
7.9
mm.
TYP
MAX.
330
13.2
22.4
6.65
10.5
2.3
4.1
8.1
MIN.
0.504
0.795
2.362
0.254
0.406
0.082
0.153
0.311
inch
TYP.
MAX.
12.992
0.519
0.882
0.262
0.414
0.090
0.161
0.319
11/14
11 Page | ||
| Páginas | Total 14 Páginas | |
| PDF Descargar | [ Datasheet 74LVQ161.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| 74LVQ161 | SYNCHRONOUS PRESETTABLE 4-BIT COUNTER | STMicroelectronics |
| 74LVQ163 | SYNCHRONOUS PRESETTABLE 4-BIT COUNTER | STMicroelectronics |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |