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PDF LS7060C Data sheet ( Hoja de datos )
| Número de pieza | LS7060C | |
| Descripción | (LS7060C / LS7061C) 32 BIT BINARY UP COUNTER | |
| Fabricantes | LSI | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de LS7060C (archivo pdf) en la parte inferior de esta página. Total 7 Páginas | ||
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LSI/CSI
LS7060C
LS7061C
U® L
LSI Computer Systems, Inc. 1235 Walt Whitman Road, Melville, NY 11747 (631) 271-0400 FAX (631) 271-0405
A3800
32 BIT BINARY UP COUNTER
WITH BYTE MULTIPLEXED THREE-STATE OUTPUTS
ADVANCE INFORMATION
January 2002
FEATURES:
• DC to 50MHz Count Frequency
• Byte Multiplexer
PIN ASSIGNMENT - TOP VIEW
• DC to 10MHz Byte Output Scan Frequency
• +4.75V to +5.25V Operation (VDD - VSS)
COUNT 1
18 V DD (+V)
• Three-State Data Outputs; Bus, TTL and CMOS Compatible
• Inputs TTL and CMOS Compatible
ALT COUNT 2
17 B4 OUT
• Unique Cascade Feature Allows Multiplexing of
Successive Bytes of Data in Sequence in Multiple
B3 OUT 3
16 B5 OUT
Counter Systems
B2 OUT 4
15 B6 OUT
• Low Power Dissipation
• LS7060C (DIP), LS7060C-S (SOIC) - See Figure 1
B1 OUT 5 LS7060C
14 B7 OUT
• LS7061C (DIP), LS7061C-S (SOIC) - See Figure 2
B0 OUT 6
13 TEST COUNT
DESCRIPTION:
The LS7060C/LS7061C are CMOS Silicon Gate, 32 bit Up
Counters. The ICs include latches, multiplexer, byte output se-
quencer, eight three-state binary data output drivers and output
www.DataSheect4Ua.csocmading logic.
RESET 7
CASCADE EN OUT 8
VSS (-V) 9
12 SCAN RESET/LOAD
11 ENABLE
10 SCAN
DESCRIPTION OF OPERATION:
32 BIT BINARY UP COUNTER - LS7060C (LS7061C)
The 32 bit static ripple through counter increments on the neg-
ative edge of the input count pulse. Maximum ripple time is 20ns
transition count of 32 ones to 32 zeros.
Guaranteed count frequency is DC to 50MHz.
See Figure 9A (9B) for Block Diagram.
FIGURE 1
PIN ASSIGNMENT - TOP VIEW
V DD (+V) 1
(COUNT) B7 IN 2
B3 OUT 3
B6 IN 4
24 B4 OUT
23 B5 OUT
22 B0 IN
21 B1 IN
COUNT, ALT COUNT (LS7060C)
Input count pulses to the 32 bit counter may be applied through
either of these two inputs. The ALT COUNT input circuitry con-
tains a Schmitt trigger network which allows proper counting with
"infinitely" long clock edges. A high applied to either of these two
inputs inhibits counting.
COUNT (LS7061C)
Input count pulses to the 32 bit counter may be applied through
this input. This input is the most significant bit of the external data
byte.
B2 OUT 5
B5 IN 6
B1 OUT 7
B4 IN 8
B0 OUT 9
R E S E T 10
CASCADE ENABLE OUT 11
Vss (-V) 12
LS7061C
20 B6 OUT
19 B2 IN
18 B7 OUT
17 B3 IN
16 TEST COUNT
15 SCAN RESET/LOAD
14 ENABLE
13 SCAN
RESET
All 32 counter bits are reset to zero when RESET is brought low
for a minimum of 20ns. RESET must be high for a minimum of
10ns before next valid count can be recorded.
TEST COUNT
Count pulses may be applied to the last 16 bits of the binary
counter through this input, as long as Bit 16 of the counter is a
low. The counter advances on the negative transition of these
pulses. This input is intended to be used for test purposes.
NOTE: LS7060C and LS7061C can directly replace LS7060 and
LS7061 in all existing applications.
7060C/61C-012102-1
FIGURE 2
LATCHES
32 bits of latch are provided for storage of counter data for the
LS7060C. 40 bits of latch are provided for the LS7061C of which
eight are for storage of a high speed external prescaling counter
and the remaining 32 are for the contents of the chip counter
data. All latches are loaded when the LOAD input is brought low
for a minimum of 10ns and kept low until a minimum of 20ns has
elapsed from previous negative edge of count pulse (ripple time).
Storage of valid data occurs when LOAD is brought high for a
minimum of 20ns before next negative edge of count pulse or
RESET.
1 page  
RESET
COUNT
LOAD
tRPW
tRR + tCPW
tRSCR
tCPW
tCR
tRSCPW
FIGURE 4. COUNTER TIMING DIAGRAM
tRPW
tRR+tCPW
tCPW
ENABLE
SCAN RESET
SCAN
A CE
EN SC RESET SC
OUTPUT DATA BUS
B CE
EN SC RESET SC
C CE
EN SC RESET SC
END OF SCAN
FIGURE 5. ILLUSTRATION OF A 3 DEVICE CASCADE
SCAN RESET
ENABLE
SCAN
CASCADE ENABLE A
CASCADE ENABLE B
CASCADE ENABLE C
(END OF SCAN)
DATA BYTE ON BUS
PACKAGE
7060C/61C-121901-5
123 4 5 1 23 4 5 123 4 5
AB C
FIGURE 6. TIMING DIAGRAM FOR THE 3 DEVICE CASCADE
5 Page | ||
| Páginas | Total 7 Páginas | |
| PDF Descargar | [ Datasheet LS7060C.PDF ] | |
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