PDF STP2230SOP Data sheet ( Hoja de datos )

Número de pieza	STP2230SOP
Descripción	Uniprocessor System Controller
Fabricantes	Sun
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No Preview Available ! DATA SHEET STP2200ABGA July 1997 USC Uniprocessor System Controller DESCRIPTION The Uniprocessor System Controller (USC) has a DRAM memory controller and functions to regulate the ﬂow of requests and data on the UPA bus. It also controls the resets going to all UPA clients. Features www.DataSheet4U.com • Controls up to eight standard SS-10/SS-20-type DRAM SIMMs • Supports various memory SIMM organizations: 16 MB, 64 MB, and 256 MB as well as dual-stacked 128-MB SIMMs • Controls and generates a number of resets for the system • Programmed via a standard 8-bit asynchronous interface (EBus) • JTAG interface allows full chip scan • 225-pin ABGA package Beneﬁts • Standard workstation memory • Flexibility • High integration • Allows design of low-cost, low-chip-count embedded systems • Ease of design and testability • Low cost The USC is used as the system controller of a complete Uniprocessor UltraSPARC system. Note: Instead of using the U2S, the USC can also be used with the UPA to PCI-bus; I/O interface controller (U2P) UPA Devices USC RIC U2S U2P XBI Abbreviations SC_UP RISC SYSIO Psycho BMX Part Number STP 2200ABGA STP2210QFP STP2220ABGA STP2222ABGA STP2230SOP Description Uniprocessor System Controller Reset/Interrupt/Clock Controller UPA to SBus I/O interface controller UPA to PCI bus I/O Interface controller Crossbar Data Path Note: This data sheet refers to the UPA to System I/O interface. The UPA to PCI bus Interface controller (U2P) can be substituted where U2S appears. 1 1 page USC Uniprocessor System Controller STP2200ABGA Crossbar Interface Signals Signal BMX_CMD1[3:0] MRB_CTRL1 MWB_CTRL1 Type O O O Duplicate of BMX_CMD0[3:0] Duplicate of MRB_CTRL0 Duplicate of MWB_CTRL0 Description EBus Signals Signal EBUS_DATA[7:0] EBUS_CS EBUS_ADDR[2:0] EBUS_RDY EBUS_WR EBUS_RD Type I/O I I O I I Condition 5-V tolerant 5-V tolerant 5-V tolerant 5-V tolerant 5-V tolerant Description Data in and data out pins - 3.3 volt output level Chip select for USC on the EBus EBus address EBus ready to the STP2001 SLAVIO- 3.3 volt output level Indicates write on EBus Indicates read on EBus Miscellaneous Signals Signal CLK+ CLK– SYS_RESET P_BUTTON_RESET X_BUTTON_RESET PLL_BYPASS JTAG_TDI JTAG_TDO JTAG_TCK JTAG_TMS JTAG_TRST DEBUG[3:0] PM_OUT Type I I I I I I I O I I I O O Condition PECL PECL 5-V tolerant 5-V tolerant 5-V tolerant 5-V tolerant 5-V tolerant 5-V tolerant 5-V tolerant Description System clock (differential) System clock (differential) Power-on reset; pulldown POR button reset XIR button reset Bypass internal PLL Test data input Test data output- 3.3 volt output level Scan clock Test mode select; pullup Reset TAP controller; pullup Debug pins Process monitor output Power and Ground Signal VDD VSS +3.3 V Ground Description July 1997 5 5 Page USC Uniprocessor System Controller STP2200ABGA AC CHARACTERISTICS Nearly all inputs and outputs are registered and are referenced to the PECL differential input clock (CLK+ and CLK–). This clock input controls an on-board PLL. These signals are clocked by the rising edge of CLK+ at the crossover between CLK+ and CLK– (where both signals are at the same voltage). All inputs are applied with a rise and fall time of 1.0 nanosecond (ns). The JTAG signals, are referenced to JTAG_TCK. They are asynchronous signals with respect to CLK+/CLK–. The following signals are asynchronous to CLK + and CLK – and the JTAG clock. They include resets and the EBus Interface signals: EBUS_ADDR[2:0] EBUS_CS EBUS_RD EBUS_WR EBUS_DATA[7:0] P_RESET X_RESET SYS_RESET JTAG_TRST AC Characteristics, UPA_CLK+ / UPA_CLK – Parameter tCYCLE tWH tWL tE tE Signal Name CLK+ /CLK– CLK+ /CLK– CLK+ /CLK– CLK+ /CLK– CLK– /CLK– Condition Rising Falling -83 Min Max 40.0 83.3 5.4 5.4 600 600 -100 Min Max 40 100.0 4.4 4.4 600 600 Units MHz ns ns ps ps July 1997 11 11 Page

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