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IA186EM Schematic ( PDF Datasheet ) - InnovASIC

Teilenummer IA186EM
Beschreibung (IA186EM / IA188EM) 8/16-Bit Microcontrollers
Hersteller InnovASIC
Logo InnovASIC Logo 




Gesamt 70 Seiten
IA186EM Datasheet, Funktion
IA186EM/IA188EM
8/16-Bit Microcontrollers
Data Sheet
www.DataSheet4U.com
Copyright ! 2004






IA186EM Datasheet, Funktion
IA186EM/IA188EM
8/16-BIT Microcontrollers
Data Sheet
As of Production Version -03
a[19:0]
ad[15:0]
ale
den_n
wr_n
wlb_n
whb_n
rd_n
Bus Interface & Control
res_n
Peripheral Control and
Registers
lcs_n/once0_n
mcs3_n/rfsh_n
ucs_n/once1_n
pcs5_n/a1
pcs6_n/a2
mcs2_n - mcs0_n
pcs3_n - pcs0_n
Chip Selects and Control
pio[31:0]
Programmable I/O
Clock and
Power Management
clkouta
clkoutb
Direct Memory Access
drq0
drq1
Interrupt Controller
Timers
int4
int3/inta1_n/irq
int2/inta0_n
int1/select_n
int0
nmi
tmrin0
tmrout0
tmrin1
tmrout1
Asynchronous Serial
Port
txd0
rxd0
cts0_n/enrx0_n
rts0_n/rtr0_n
Synchronous Serial Port
sclk
sden0
sden1
sdata
Instruction Decode
and Execution
Figure 1. IA186/88EM Block Diagram
NOTE
See pin descriptions for pins that share other functions with PIO pins.
pwd, int5, int6, rts1_n/rtr1_n, and cts1_n/enrx1_n are multiplexed with int2_n/inta0_n, drq0_n,
drq0_n, pcs3_n, and pcs2_n respectively.
3737 Princeton NE, Ste 130 • Albuquerque, NM 87107 • Tel 505.883.5263 • Fax 505.883.5477 • www.Innovasic.com

6 Page









IA186EM pdf, datenblatt
IA186EM/IA188EM
8/16-BIT Microcontrollers
Data Sheet
As of Production Version -03
MDRAM (0e0h) - The Memory Partition Register holds the A19-A13 address bits of the 20-bit base
refresh address.
The MDRAM register contains 0000h at reset.
15 14 13 12 11 10
9 876543210
M [6:0]
000000000
M [6:0] (bits 15-9) – Upper bits corresponding to address bits a19-a13 of the 20-Bit memory refresh
address. These bits are not available on the a19-a0 bus. When using PSRAM mode, M6-M0 must be
programmed to 0000000b.
Reserved [8:0] (bits 8-0) – Reserved. These bits read back as 0.
D1CON (0dah) - DMA CONtrol Registers.
D0CON (0cah)
DMA Control Registers control operation of the two DMA channels. The D0CON and D1CON registers
are undefined at reset, except ST that is set to 0.
15
14 13
12
11 10 9 8 7 6 5 4
3 210
DM/IOn DDEC DINC SM/IOn SDEC SINC TC INT SYN1- P TDRQ Res CHG ST Bn/W
SYN0
DM/IOn (bit 15) – Destination Address Space Select selects memory or I/O space for the destination
address. When DM/IO is set to 1, the destination address is in memory space. When set to 0, the
destination address is in I/O space.
DDEC (bit 14) – Destination Decrement automatically decrements the destination address after each
transfer when set to 1. The address is decremented by 1 or 2, depending on the byte/word bit (Bn/W,
bit 0). The address does not change if the increment and decrement bits are set to the same value (00b
or 11b).
DINC (bit 13) – Destination Increment, when set to 1, automatically increments the destination
address after each transfer. The address is incremented by 1 or 2, depending on the byte/word bit
(Bn/W, bit 0). The address does not change if the increment and decrement bits are set to the same
value (00b or 11b).
SM/IOn (bit 12) – Source Address Space Select selects memory or I/O space for the source address.
When SM/IOn is set to 1, the source address is in memory space, while when 0, the source address is
in I/O space.
3737 Princeton NE, Ste 130 • Albuquerque, NM 87107 • Tel 505.883.5263 • Fax 505.883.5477 • www.Innovasic.com

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