Datenblatt-pdf.com


3D7408 Schematic ( PDF Datasheet ) - Data Delay Devices

Teilenummer 3D7408
Beschreibung MONOLITHIC 8-BIT PROGRAMMABLE DELAY LINE
Hersteller Data Delay Devices
Logo Data Delay Devices Logo 




Gesamt 7 Seiten
3D7408 Datasheet, Funktion
www.DataSheet4U.com
MONOLITHIC 8-BIT
PROGRAMMABLE DELAY LINE
(SERIES 3D7408)
3D7408
data
delay
3
®
devices, inc.
FEATURES
PACKAGES
All-silicon, low-power CMOS technology
TTL/CMOS compatible inputs and outputs
Vapor phase, IR and wave solderable
Auto-insertable (DIP pkg.)
Low ground bounce noise
Leading- and trailing-edge accuracy
Increment range: 0.25 through 5.0ns
Delay tolerance: 1% (See Table 1)
Temperature stability: ±3% typical (0C-70C)
Vdd stability: ±1% typical (4.75V-5.25V)
Minimum input pulse width: 10% of total
delay
Programmable via 3-wire serial or 8-bit
parallel interface
IN 1 16 VDD
AE 2 15 OUT
SO/P0 3 14 MD
P1 4 13 P7
P2 5 12 P6
P3 6 11 SC
P4 7 10 P5
GND 8 9 SI
3D7408 DIP
3D7408G Gull Wing
(300 Mil)
IN
AE
SO/P0
P1
P2
P3
P4
GND
1 16
2 15
3 14
4 13
5 12
6 11
7 10
89
3D7408S
SOIC
(300 Mil)
VDD
OUT
MD
P7
P6
SC
P5
SI
(For mechanical data, see Case Dimensions document)
FUNCTIONAL DESCRIPTION
PIN DESCRIPTIONS
The 3D7408 Programmable 8-Bit Silicon Delay Line product
family consists of 8-bit, user-programmable CMOS silicon
integrated circuits. Delay values, programmed either via the
serial or parallel interface, can be varied over 255 equal steps
ranging from 250ps to 5.0ns inclusively. Units have a typical
inherent (zero step) delay of 12ns to 17ns (See Table 1). The
input is reproduced at the output without inversion, shifted in time
as per user selection. The 3D7408 is TTL- and CMOS-
compatible, capable of driving ten 74LS-type loads, and features
both rising- and falling-edge accuracy.
IN Signal Input
OUT Signal Output
MD Mode Select
AE Address Enable
P0-P7 Parallel Data Input
SC Serial Clock
SI Serial Data Input
SO Serial Data Output
VCC +5 Volts
GND Ground
The all-CMOS 3D7408 integrated circuit has been designed as a reliable, economic alternative to hybrid
TTL programmable delay lines. It is offered in a standard 16-pin auto-insertable DIP and a space saving
surface mount 16-pin SOIC.
TABLE 1: PART NUMBER SPECIFICATIONS
PART
NUMBER
3D7408-0.25
3D7408-0.5
3D7408-1
3D7408-2
3D7408-3
3D7408-4
3D7408-5
DELAYS AND TOLERANCES
Step 0
Step 255 Delay
Delay (ns) Delay (ns) Increment (ns)
12 ± 2 75.75 ± 4.0
0.25 ± 0.15
12 ± 2 139.5 ± 4.0
0.50 ± 0.25
12 ± 2 267.0 ± 5.0
1.00 ± 0.50
14 ± 2 522.0 ± 6.0
2.00 ± 1.00
17 ± 2 782.0 ± 8.0
3.00 ± 1.50
17 ± 2 1037 ± 9.0
4.00 ± 2.00
17 ± 2 1292 ± 10
5.00 ± 2.50
Max Operating
Frequency
6.25 MHz
3.15 MHz
1.56 MHz
0.78 MHz
0.52 MHz
0.39 MHz
0.31 MHz
INPUT RESTRICTIONS
Absolute Max Min Operating
Oper Freq
P.W.
90 MHz
80.0 ns
45 MHz
160.0 ns
22 MHz
320.0 ns
11 MHz
640.0 ns
7.5 MHz
960.0 ns
5.5 MHz
1280.0 ns
4.4 MHz
1600.0 ns
Absolute Min
Oper P.W.
5.5 ns
11.0 ns
22.0 ns
44.0 ns
66.0 ns
88.0 ns
110.0 ns
NOTES: Any delay increment between 0.25 and 5.0 ns not shown is also available.
All delays referenced to input pin
Doc #96003
12/2/96
DATA DELAY DEVICES, INC.
3 Mt. Prospect Ave. Clifton, NJ 07013
©1996 Data Delay Devices
1






3D7408 Datasheet, Funktion
3D7408
DEVICE SPECIFICATIONS
TABLE 3: ABSOLUTE MAXIMUM RATINGS
PARAMETER
SYMBOL MIN
MAX UNITS NOTES
DC Supply Voltage
VDD
-0.3 7.0
V
Input Pin Voltage
VIN -0.3 VDD+0.3 V
Input Pin Current
IIN -10 10 mA 25C
Storage Temperature
TSTRG
-55
150
C
Lead Temperature
TLEAD
300 C 10 sec
TABLE 4: DC ELECTRICAL CHARACTERISTICS
(0C to 70C, 4.75V to 5.25V)
PARAMETER
Static Supply Current*
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
High Level Output Current
SYMBOL
IDD
VIH
VIL
IIH
IIL
IOH
Low Level Output Current
IOL
Output Rise & Fall Time
TR & TF
*IDD(Dynamic) = CLD * VDD * F
where: CLD = Average capacitance load/line (pf)
F = Input frequency (GHz)
MIN
2.0
-4.0
4.0
MAX
40
0.8
1.0
1.0
2
UNITS
mA
V
V
µA
µA
mA
mA
ns
NOTES
VIH = VDD
VIL = 0V
VDD = 4.75V
VOH = 2.4V
VDD = 4.75V
VOL = 0.4V
CLD = 5 pf
Input Capacitance = 10 pf typical
Output Load Capacitance (CLD) = 25 pf max
TABLE 5: AC ELECTRICAL CHARACTERISTICS
(0C to 70C, 4.75V to 5.25V)
PARAMETER
SYMBOL MIN TYP MAX
UNITS
NOTES
Clock Frequency
Enable Width
fC
tEW 10
80 MHz
ns
Clock Width
Data Setup to Clock
Data Hold from Clock
Data Setup to Enable
tCW
tDSC
tDHC
tDSE
10
10
3
10
ns
ns
ns
ns
Data Hold from Enable
tDHE
3
ns
Enable to Serial Output Valid
Enable to Serial Output High-Z
Clock to Serial Output Valid
Clock to Serial Output Invalid
tEQV
tEQZ
tCQV
tCQX
10
20 ns
20 ns
20 ns
ns
Enable Setup to Clock
Enable Hold from Clock
Parallel Input Valid to Delay Valid
tES 10
tEH 10
tPDV 20 40
ns
ns
ns
1
Parallel Input Change to Delay Invalid
tPDX
0
ns 1
Enable to Delay Valid
tEDV
35 45
ns
1
Enable to Delay Invalid
tEDX
0
ns 1
Input Pulse Width
Input Period
tWI
Period
8
20
% of Total Delay See Table 1
% of Total Delay See Table 1
Input to Output Delay
tPLH, tPHL
ns See Table 2
NOTES: 1 - Refer to PROGRAMMED DELAY (ADDRESS) UPDATE section
Doc #96003
DATA DELAY DEVICES, INC.
12/2/96
Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com
6

6 Page







SeitenGesamt 7 Seiten
PDF Download[ 3D7408 Schematic.PDF ]

Link teilen




Besondere Datenblatt

TeilenummerBeschreibungHersteller
3D7408MONOLITHIC 8-BIT PROGRAMMABLE DELAY LINEData Delay Devices
Data Delay Devices

TeilenummerBeschreibungHersteller
CD40175BC

Hex D-Type Flip-Flop / Quad D-Type Flip-Flop.

Fairchild Semiconductor
Fairchild Semiconductor
KTD1146

EPITAXIAL PLANAR NPN TRANSISTOR.

KEC
KEC


www.Datenblatt-PDF.com       |      2020       |      Kontakt     |      Suche