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Teilenummer | 74HC4852 |
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Beschreibung | Dual 4-channel analog multiplexer/demultiplexer | |
Hersteller | NXP Semiconductors | |
Logo | ||
Gesamt 20 Seiten 74HC4852
Dual 4-channel analog multiplexer/demultiplexer with
injection-current effect control
Rev. 02 — 30 May 2007
Product data sheet
1. General description
www.DataSheet4U.com
2. Features
The 74HC4852 is a high-speed Si-gate CMOS device and is specified in compliance with
JEDEC standard no. 7A.
The 74HC4852 is a dual 4-channel analog multiplexer or demultiplexer with common
select inputs (S0 and S1). Both multiplexers have a common active LOW enable input (E),
four independent inputs/outputs (pins nY0 to nY3) and a common input/output (pin nZ).
The device features injection-current effect control, which has excellent value in
automotive applications where voltages in excess of the supply voltage are common.
With E LOW, two of the eight switches are selected (low impedance ON-state) by S0 and
S1. With E HIGH, all switches are in the high-impedance OFF-state, independent of S0
and S1.
The injection-current effect control allows signals at disabled analog input channels to
exceed the supply voltage without affecting the signal of the enabled analog channel. This
eliminates the need for external diode/resistor networks typically used to keep the analog
channel signals within the supply-voltage range.
I Injection-current cross coupling < 1 mV/mA
I Wide supply voltage range from 2.0 V to 6.0 V
I ESD protection:
N HBM JESD22-A114E Class 2 exceeds 2000 V
N MM JESD22-A115-A exceeds 200 V
N CDM JESD22-C101C exceeds 1000 V
I Latch-up performance exceeds 100 mA per JESD 78 Class II
I Low ON-state resistance:
N 400 Ω (typical) at VCC = 2.0 V
N 215 Ω (typical) at VCC = 3.0 V
N 120 Ω (typical) at VCC = 3.3 V
N 76 Ω (typical) at VCC = 4.5 V
N 59 Ω (typical) at VCC = 6.0 V
NXP Semiconductors
74HC4852
4-channel analog MUX/DEMUX with injection-current effect control
9. Recommended operating conditions
Table 5.
Symbol
VCC
VI
VSW
Tamb
∆t/∆V
Recommended operating conditions
Parameter
supply voltage
input voltage
switch voltage
ambient temperature
input transition rise and fall rate
Conditions
VCC = 2.0 V
VCC = 3.0 V
VCC = 3.3 V
VCC = 4.5 V
VCC = 6.0 V
10. Static characteristics
Table 6. RON resistance
For test circuit see Figure 8.
Symbol Parameter
Tamb = 25 °C
RON(peak) ON resistance (peak)
∆RON
ON resistance mismatch between
channels
Tamb = −40 °C to +85 °C
RON(peak) ON resistance (peak)
Conditions
VI = VCC to GND; E = VIL
VCC = 2.0 V; ISW = 2 mA
VCC = 3.0 V; ISW ≤ 2 mA
VCC = 3.3 V; ISW ≤ 2 mA
VCC = 4.5 V; ISW ≤ 2 mA
VCC = 6.0 V; ISW ≤ 2 mA
VI = 0.5 × VCC; E = VIL
VCC = 2.0 V; ISW = 2 mA
VCC = 3.0 V; ISW ≤ 2 mA
VCC = 3.3 V; ISW ≤ 2 mA
VCC = 4.5 V; ISW ≤ 2 mA
VCC = 6.0 V; ISW ≤ 2 mA
VI = VCC to GND; E = VIL
VCC = 2.0 V; ISW = 2 mA
VCC = 3.0 V; ISW ≤ 2 mA
VCC = 3.3 V; ISW ≤ 2 mA
VCC = 4.5 V; ISW ≤ 2 mA
VCC = 6.0 V; ISW ≤ 2 mA
Min Typ Max Unit
2.0 - 6.0 V
0-
0-
−40 -
VCC
VCC
+125
V
V
°C
- 6.0 1000 ns/V
- 6.0 800 ns/V
- 6.0 800 ns/V
- 6.0 500 ns/V
- 6.0 400 ns/V
Min Typ Max Unit
- 400 650 Ω
- 215 330 Ω
- 120 270 Ω
- 76 210 Ω
- 59 195 Ω
- 4 10 Ω
-2 8 Ω
-2 8 Ω
-2 8 Ω
-3 9 Ω
--
--
--
--
--
670 Ω
360 Ω
305 Ω
240 Ω
220 Ω
74HC4852_2
Product data sheet
Rev. 02 — 30 May 2007
© NXP B.V. 2007. All rights reserved.
6 of 20
6 Page NXP Semiconductors
74HC4852
4-channel analog MUX/DEMUX with injection-current effect control
Table 9. Dynamic characteristics …continued
GND = 0 V; CL = 50 pF; RL = 10 kΩ unless specified otherwise; for test circuit see Figure 12.
Symbol Parameter
Conditions
25 °C
−40 °C to +85 °C −40 °C to +125 °C Unit
Min Typ Max Min Max Min Max
VCC = 6.0 V
tpd propagation delay see Figure 10
[1]
nZ, nYn to nYn, nZ
1.5 2.5 10.2 0.9
11
0.9
12 ns
Sn to nZ, nYn
2.4 4.8 12.6 1.6 14.5 1.6 16.5 ns
ten enable time see Figure 11
E to nZ, nYn
[2]
3.2 5.6 39 2.2
40
2.2
40 ns
tdis disable time see Figure 11
E to nZ, nYn
[3]
14.4 57.9
78
13.5
80
13.0
80 ns
Power dissipation capacitance
CPD power dissipation per channel
[4]
capacitance
VCC = 3.3 V
- 42 -
-
-
-
- pF
VCC = 5.0 V
- 47 -
-
-
-
- pF
[1] tpd is the same as tPLH and tPHL.
[2] ten is the same as tPZH and tPZL.
[3] tdis is the same as tPLZ and tPHZ.
[4] CPD is used to determine the dynamic power dissipation (PD in µW):
PD = CPD × VCC2 × fi + ∑{(CL + Csw) × VCC2 × fo} where:
fi = input frequency in MHz;
fo = output frequency in MHz;
∑{(CL + Csw) × VCC2 × fo} = sum of outputs;
CL = output load capacitance in pF;
Csw = switch capacitance in pF;
VCC = supply voltage in V.
12. Waveforms
VI
nZ, nYn or Sn
input
GND
VM
tPLH
VM
tPHL
VOH
nYn or nZ
input
VOL
VM
VM
001aag102
Measurement points are given in Table 10.
Logic levels: VOL and VOH are typical output voltage levels that occur with the output load.
Fig 10. Input (nZ, nYn or Sn) to output (nYn, nZ) propagation delays
74HC4852_2
Product data sheet
Rev. 02 — 30 May 2007
© NXP B.V. 2007. All rights reserved.
12 of 20
12 Page | ||
Seiten | Gesamt 20 Seiten | |
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