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STA304A Schematic ( PDF Datasheet ) - STMicroelectronics

Teilenummer STA304A
Beschreibung DIGITAL AUDIO PROCESSOR
Hersteller STMicroelectronics
Logo STMicroelectronics Logo 




Gesamt 30 Seiten
STA304A Datasheet, Funktion
STA304A
DIGITAL AUDIO PROCESSOR WITH MULTICHANNEL DDX™
„ STA304AEND TO END DIGITAL AUDIO
INTEGRATED SOLUTION
„ · DSP Functions:
- DIGITAL VOLUME CONTROL
- SOFT MUTE
- BASS and TREBLE
- PARAMETRIC EQ PER CHANNEL
- BASS MANAGEMENT FOR SUBWOOFER
- AUTO MUTE ON ZERO INPUT DETECTION
„ 4+1 DIRECT DIGITAL AMPLIFICATION
(DDX™) OUTPUT CHANNELs
„ 6 CHANNELs PROGRAMMABLE SERIAL
OUTPUT INTERFACE (by default I2S)
„ 4 CHANNELs PROGRAMMABLE SERIAL
INPUT INTERFACE (by default I2S)
„ STEREO S/PDIF INPUT INTERFACE
„ Intel AC'97 LINK (rev. 2.1) INPUT INTERFACE
FOR AUDIO AND CONTROL
„ ON CHIP AUTOMATIC INPUT SAMPLING
FREQUENCY DETECTION
„ 100 dB SNR SAMPLE RATE CONVERTER
(1KHz SINUSOIDAL INPUT)
„ I2C CONTROL BUS
-„ LOW POWER 3.3V CMOS TECHNOLOGY
)BLOCK DIAGRAM
t(sSA SCL SDA
11 10 9
ucLRCKI/ SYNC
dBICKI / BIT_CL
3
4
roSDI_1 / SDATA_OUT 1
SDI_2 / SDATA_IN 2
PRXP 18
bsolete RXN 19
I2S
S/PDIF
I2C
SRC
AC`97
TQFP44
ORDERING NUMBER: STA304A
t(s)„ EMBEDDED PLL FOR INTERNAL CLOCK
cGENERATION (1024x48 kHz = 49.152 MHz)
u„ 6.144 MHz EXTERNAL INPUT CLOCK OR
dBUILT-IN INDUSTRY STANDARD XTAL
roOSCILLATOR
„ VARIABLE DIGITAL GAIN UP TO 24dB
P(0.75dB STEP)
te1.0 DESCRIPTION
leThe STA304A Digital Audio Processor is a single
ochip device implementing end to end digital solution
sfor audio application. In conjunction with STA500
bpower bridge it gives the full digital DSP-to-power
Ohigh quality chain with no need for audio Digital-to-
Analog converters between DSP and power stage.
ROM
DSP
RAM
DDX
I2S
29 LEFT_A
30 LEFT_B
27 RIGHT_A
28 RIGHT_B
33 SLEFT_A
34 SLEFT_B
23 SRIGHT_A
24 SRIGHT_B
21 LFE_A
22 LFE_B
43 LRCKO
43 BICKO
43 SDO_1
43 SDO_2
43 SDO_3
RESET 7
PLL
PowerDown
35 EAPD
April 2010
14 15
XTI XTO
43
CKOUT
44
PWDN
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STA304A Datasheet, Funktion
STA304A
DC ELECTRICAL CHARACTERISTICS
Symbol
Parameter
Test Condition
Min. Typ. Max. Unit Note
Vil Low Level Input Voltage
0.2*VDD V
Vih High Level Input Voltage
0.8*VDD
V
Vol Low Level Output Voltage
Iol = X mA
0.4*VDD V
1,2
Voh High Level Output Voltage
0.85*VDD
V 1,2
Note 1: Takes into account 200mV voltage drop in both supply lines
Note 2: X is the source/sinc current under worst case conditions and is reflected in the name of the I/O cell according to the drive capability.
Ipu Pull-up current
Vi = 0V;
VDD = 3.3V
-25 -66 -125 µA
1
Rpu Equivalent Pull-up resistance
)TR Reset Active Time
ct(sTCK Master Clock Period
50
2·TCK
--------1---------
49.152
K
ns
ns
duNote 1: Min condition: Vdd = 3.0V, 125°C Min process; Max. condition: Vdd = 3.6 V, -20°C max process.
roDIGITAL CHARACTERISTICS-SPDIF RECEIVER (RXP,RXN pins only, SPDIF - MODE = ANALOG)
PZIN Input Resistance
teVTH Dufferential Input Voltage
200
leVHY Input Hysteresis
50
k
mV
mV
so2.0 AC’97 BANK REGISTER OVERVIEW
bThe AC `97 interface is compliant to ‘Audio Codec `97 – Revision 2.1’ specification, as far as the protocol used.
OAll the registers described in this specification, including Standard, Vendor Reserved and Extended Audio (AC
`97 2.0) registers, are available in this device, but just relevant registers which are described in paragraph 11
-(Register Summary) are implemented.
t(s)The ATE mode feature has been implemented for test purpose: for related details refer to the ‘Audio Codec `97
– Revision 2.1’ specification.
uc2.1 Reading AC `97 Registers
dSince the AC`97 register bank has been implemented as a contiguous RAM space (from a DSP point of view)
rothe content of the RAM itself will be returned as the result of a read operation. This should be followed as a
general rule of thumb but, where not possible, a different approach has been used. Hereby is a list of the reg-
Pisters, and bits, that do not follow this rule or that have a particular handling:
lete• CodecID_0, CodecID_1:
These two bit are respectively bits 14 and 15 of registers 28h (Extended Audio ID) and 3Ch (EWxtended
o Modem ID). When a read operation of these registers is performed the returned value is based on the status
bs of the SA pin: CodecID_0 report the status of SA pin, CodecID_1 always report 0. Other bits of these regis-
ters return the related RAM register contents. Also note that the status of the SA pin is not readable by the
DSP.
• PR4:
The bit 12 of register 26h (Powerdown, ctrl/start) is used to set the AC`97 BIT_CLK and SDATA_IN signal
to a low state. In response to a Warmers the status of this bit is set back to its default 0 value. In response
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6 Page









STA304A pdf, datenblatt
STA304A
specification. The following table summarize the slot usage for each one the these frequencies:
Freq. Slot 3 Slot 4 Slot 6 Slot 7 Slot 8 Slot 9 Slot 10
Slot 11
Slot 12
48 Left Right Center Surr.L Surr.R LFE
44.1 Left Right
Surr.L Surr.R
88.2 * Left Right Center
Left (n+1) Right (n+1) Center (n+1)
96 Left Right Center
Left (n+1) Right (n+1) Center (n+1)
* Slots 3, 4 and 6 are always requested. Slots 10, 11 and 12 are requested only when needed.
The following table summarize the different input possibilities:
Input from
Channels
Available Freq. (KHz)
Bypass
Notes
I2S (Master)
4
48 Yes Bypass is user selectable
t(s)I2S (Slave)
4
32..96
No
S/PDIF
2
32..96
No
ucAC`97
6
48 Yes * Left, Right, SL, SR, Center, LFE
dAC`97
3
96 No Left, Right, Center
roAC`97
4
44.1 (VRA)
No Left, Right, SL, SR
PAC`97
3
88.2 (VRA)
No Left, Right, Center
te* In this configuration the BYPASS is always active, regardless SRC_Bypass bit in reg. 5Ah
le7.0 PLL
soIn order to generate the internal 49.152 MHz clock a low-jitter PLL has been included in the device. It can be config-
bured to work either with a multiplication factor of x8 or x2, in order to fit an external frequency reference of 6.144 MHz
or, respectively, 24.576 MHz. This could be useful when the device is configured to work in AC`97 slave mode where
Othe master clock is 24.576 MHz. To select the multiplication factor the PLL_Factor bit can be used.
-Using the PLL_Bypass bit the PLL section can be bypassed, allowing direct connection of the internal clock to
)the XTI pin. When this option is selected an external frequency of 49.152 MHz should be provided to the device.
t(sIn this condition the PLL is automatically powered-down.
c8.0 POWERDOWN MANAGEMENT
uThe powerdown capability and its logic behaviour is shown in Figure 7 - Powerdown management . Basically
dthere are three powerdown requests which comes from the extern of the device and will cause a different pow-
roerdown condition:
- External PWDN pin – this signal will turn-off the device which, as a consequence, will enter the power-
Pdown mode (all the device clocks are stopped). The device will exit this state as soon as the PWDN pin
teis deasserted.
- PR5 bit (reg. 26h, bit 13) – Setting this bit will cause a partial powerdown of the device: infact all the clocks
lewill be suspended, except that used to keep the AC97 and I2C cells alive. In this way, using either of these
o input interfaces, it’ll be possible to resume from this state simply resetting the PR5 bit.
bs - EAPD bit (reg.26h, bit 15) – The External Amplifier PowerDown bit controls the state of the related pin
(EAPD) which, in turn, is used to switch off the external power chip.
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