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PDF MT8931C Data sheet ( Hoja de datos )
| Número de pieza | MT8931C | |
| Descripción | Subscriber Network Interface Circuit | |
| Fabricantes | Zarlink Semiconductor | |
| Logotipo |  |
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CMOS ST-BUS FAMILY MT8931C
Subscriber Network Interface Circuit
Data Sheet
Features
• ETS 300-012, CCITT I.430 and ANSI T1.605
S/T interface
• Full-duplex 2B+D, 192 kbit/s transmission
• Link activation/deactivation
• D-channel access contention resolution
• Point-to-point, point-to-multipoint and star
configurations
• Master (NT)/Slave (TE) modes of operation
• Exceeds loop length requirements
• Complete loopback testing capabilities
• On chip HDLC D-channel protocoller
• 8 bit Motorola/Intel microprocessor interface
• Microprocessor-controlled operation
• Zarlink ST-BUS interface
• Low power CMOS technology
• Single 5 volt power supply
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Applications
• ISDN NT1
• ISDN S or T interface
• ISDN Terminal Adaptor (TA)
• Digital sets (TE1) - 4 wire ISDN interface
• Digital PABXs, Digital Line Cards (NT2)
ISSUE 4
November 1997
Ordering Information
MT8931CE 28 Pin Plastic DIP
MT8931CP 44 Pin PLCC
-40°C to +85°C
Description
The MT8931C Subscriber Network Interface Circuit
(SNIC) implements the ETSI ETS 300-012, CCITT
I.430 and ANSI T1.605 Recommendations for the
ISDN S and T reference points. Providing point-to-
point and point-to-multipoint digital transmission, the
SNIC may be used at either end of the subscriber
line (NT or TE).
An HDLC D-channel protocoller is included and
controlled through a Motorola/Intel microprocessor
port.
The MT8931C is fabricated in Zarlink’s CMOS
process.
DSTi
DSTo
F0od
C4b
F0b
STAR/Rsto
XTAL1/NT
XTAL2/NC
ST-BUS
Interface
Timing
and
Control
D-channel Priority
Mechanism
PLL
HDLC
Transceiver
S-Bus
Link
Interface
Link
Activation
Controller
LTx
VBias
LRx
VDD
Microprocessor Interface
VSS
Rsti HALF
AD0-7
R/W/WR
DS/RD
AS/ALE
CS
IRQ/NDA
Figure 1 - Functional Block Diagram
1
1 page  
Data Sheet
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MT8931C
The B1 and B2 channels each have a bandwidth of
64 kbit/s and are used to carry PCM voice or data
across the network.
The D-channel is primarily intended to carry
signalling information for circuit switching through
the ISDN network. The SNIC provides the capability
of having a 16 kbit/s or full 64 kbit/s D-channel by
allocating the B1-channel timeslot to the D-channel.
Access to the depacketized D-channel is only
granted through the parallel microprocessor port.
The C-channel provides a means for the system to
control and monitor the functionality of the SNIC.
This control/status channel is accessed by the
system through the ST-BUS or microprocessor port.
The C-channel provides access to two registers
which provide complete control over the state
activation machine, the D-channel priority
mechanism as well as the various maintenance
functions. A detailed description of these registers is
discussed in the microprocessor port interface.
Line Code
The line code used on the S-interface is a Pseudo
ternary code with 100% pulse width as seen in
Figure 5 below. Binary zeros are represented as
marks on the line and successive marks will
alternate in polarity.
BINARY
VALUE
0 1 00 01 0 01 1
LINE
SIGNAL
Violation
Figure 5 - Alternate Zero Inversion Line Code
A mark which does not adhere to the alternating
polarity is known as a bipolar violation.
Figure 4 - ST-BUS Channel Assignment
5
5 Page 
Data Sheet
situation is when the system is trying to synchronize
two nodes of a synchronous network. This allows
multiple TEs to share a common ST-BUS timebase.
The synchronization of the loops is established by
using the clock signals produced by a local TE as an
input timing source to the NT slave.
Adaptive Timing Operation
On power-up or after a reset, the SNIC in NT mode is
set to operate in fixed timing. To switch to adaptive
timing, the user should:
1) set the DR bit to 1
2) set the Timing bit to 1 in the C-channel
Control Register
3) wait for 100 ms period
4) proceed in using the AR and DR bits as
desired
Switching from adaptive timing mode is completed
by resetting the Timing bit.
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ST-BUS Interface
MT8931C
The ST-BUS is a synchronous time division
multiplexed serial bussing scheme with data streams
operating at 2048 kbit/s configured as 32, 64 kbit/s
channels (refer to Fig. 11). Synchroni-zation of the
data transfer is provided from a frame pulse which
identifies the frame boundaries and repeats at an 8
kHz rate. Figure 4 shows how the frame pulse
(F0b) defines the ST-BUS frame boundaries. All
data is clocked into the device on the rising edge of
the 4096 kHz clock (C4b) three quarters of the way
into the bit cell, while data is clocked out on the
falling edge of the 4096 kHz clock at the start of the
bit cell.
All timing signals (i.e. F0b & C4b) are identified as
bidirectional (denoted by the terminating b). The
I/O configuration of these pins is controlled by the
mode of operation (NT or TE). In the NT mode, all
synchronized signals are supplied from an external
source and the SNIC uses this timing while
transferring information to and from the S or
ST-BUS. In the TE mode, an on-board analog
phase-locked loop extracts timing from the received
data on the S-Bus and generates the system
4096 kHz (C4b) and frame pulse (F0b). The
analog phase-locked loop also maintains proper
phase relation between the timing signals as well as
ST-BUS Clock
ST-BUS
Stream
System
Frame Pulse
Active on
Channel 0 - 3
MT8931C
NT
Active on
Channels 4 - 7
Active on
Channels 8 - 11
Active on
Channels 12 - 15
MT8931C
NT
MT8931C
NT
MT8931C
NT
F0b
F0od
F0b
F0od
F0b
F0od
F0b
F0od
System
Frame Pulse
Input
ST-BUS Stream
to TE
to TE
to TE
to TE
to TE
Figure 13 - Daisy Chaining the SNIC
to TE
MT8931C
NT
VDD
STAR
F0b
DSTi
MT8931C
NT
STAR
F0b
DSTi
MT8931C
NT
STAR
F0b
DSTi
DSTo
MT8931C
NT
STAR
F0b
DSTi
to TE
Output
ST-BUS Stream
to TE
Figure 14 - NT in Star Configuration
11
11 Page | ||
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| PDF Descargar | [ Datasheet MT8931C.PDF ] | |
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