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X9418 Schematic ( PDF Datasheet ) - Intersil Corporation

Teilenummer X9418
Beschreibung Dual Digitally Controlled Potentiometers
Hersteller Intersil Corporation
Logo Intersil Corporation Logo 




Gesamt 20 Seiten
X9418 Datasheet, Funktion
®
Data Sheet
X9418
Low Noise/Low Power/2-Wire Bus
October 12, 2006
FN8194.3
Dual Digitally Controlled Potentiometers
(XDCP™)
FEATURES
• Two potentiometers in one package
• 2-wire serial interface
• Register oriented format
—Direct Read/Write/Transfer Wiper Position
—Store as many as Four Positions per
Potentiometer
• Power supplies
—VCC = 2.7V to 5.5V
—V+ = 2.7V to 5.5V
—V– = -2.7V to -5.5V
• Low power CMOS
—Standby current < 1µA
—Ideal for Battery Operated Applications
• High reliability
—Endurance–100,000 Data Changes per Bit per
Register
—Register Data Retention–100 years
• 8-bytes of nonvolatile memory
• 2.5kΩ, 10kΩ resistor array
www.DataSheet4U.com Resolution: 64 taps each potentiometer
• 24-pin plastic DIP, 24-lead TSSOP and 24-lead
SOIC packages
• Pb-Free plus anneal available (RoHS compliant)
BLOCK DIAGRAM
VCC
VSS
V+
V-
WP
SCL
SDA
A0
A1
A2
A3
Interface
and
Control
Circuitry
8
Data
DESCRIPTION
The X9418 integrates two digitally controlled
potentiometers (XDCP) on a monolithic CMOS
integrated microcircuit.
The digitally controlled potentiometer is implemented
using 63 resistive elements in a series array. Between
each element are tap points connected to the wiper
terminal through switches. The position of the wiper on
the array is controlled by the user through the 2-wire
bus interface. Each potentiometer has associated with
it a volatile Wiper Counter Register (WCR) and 4
nonvolatile Data Registers (DR0:DR3) that can be
directly written to and read by the user. The contents
of the WCR controls the position of the wiper on the
resistor array through the switches. Power up recalls
the contents of DR0 to the WCR.
The XDCP can be used as a three-terminal
potentiometer or as a two-terminal variable resistor in
a wide variety of applications including control,
parameter adjustments, and signal processing.
R0 R1
R2 R3
Wiper
Counter
Register
(WCR)
VH0/RH0
VL0/RL0
VW0/RW0
R0 R1
R2 R3
Wiper
Counter
Register
(WCR)
Resistor
Array
XDCP1
VW1/RW1
VH1/RH1
VL1/RL1
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
XDCP is a trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005, 2006. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.






X9418 Datasheet, Funktion
X9418
Table 1. Instruction Set
Instruction Set
Instruction
Read Wiper Counter
Register
Write Wiper Counter
Register
Read Data Register
Write Data Register
XFR Data Register to
Wiper Counter Register
I3 I2 I1 I0 R1 R0 P1 P0
Operation
1 0 0 1 0 0 0 1/0 Read the contents of the Wiper Counter Register
pointed to by P0
1 0 1 0 0 0 0 1/0 Write new value to the Wiper Counter Register
pointed to by P0
1 0 1 1 1/0 1/0 0 1/0 Read the contents of the Data Register pointed to by
P0 and R1 - R0
1 1 0 0 1/0 1/0 0 1/0 Write new value to the Data Register pointed to by
P0 and R1 - R0
1 1 0 1 1/0 1/0 0 1/0 Transfer the contents of the Data Register pointed to
by P0 and R1 - R0 to its associated Wiper Counter
Register
XFR Wiper Counter
1 1 1 0 1/0 1/0 0 1/0 Transfer the contents of the Wiper Counter Register
Register to Data Register
pointed to by P0 to the Data Register pointed to by
R1 - R0
Global XFR Data
0 0 0 1 1/0 1/0 0 0 Transfer the contents of the Data Registers pointed
Registers to Wiper
Counter Registers
to by R1 - R0 of both pots to their respective Wiper
Counter Registers
Global XFR Wiper
Counter Registers to
Data Register
Increment/Decrement
Wiper Counter Register
1 0 0 0 1/0 1/0 0 0 Transfer the contents of both Wiper Counter
Registers to their respective data Registers pointed
to by R1 - R0 of both pots
0 0 1 0 0 0 0 1/0 Enable Increment/decrement of the Wiper Counter
Register pointed to by P0
Note: (7) 1/0 = data is one or zero
Figure 4. Three-Byte Instruction Sequence
SCL
SDA
S 0 1 0 1 A3 A2 A1 A0 A I3 I2 I1 I0 R1 R0 0 P0 A 0 0 D5 D4 D3 D2 D1 D0 A S
TCC
CT
AK K
KO
RP
T
Figure 5. Increment/Decrement Instruction Sequence
SCL
SDA
XX
S 0 1 0 1 A3 A2 A1 A0 A I3 I2 I1 I0 R1 R0 0 P0 A I I
T C CNN
A K KCC
R 12
T
ID
N
C
E
C
n1
DS
E
C
T
O
nP
6 FN8194.3
October 12, 2006

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X9418 pdf, datenblatt
X9418
D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.)
Symbol
ICC1
ICC2
ISB
ILI
ILO
VIH
VIL
VOL
Parameter
VCC supply current
(nonvolatile write)
VCC supply current
(move wiper, write, read)
VCC current (standby)
Input leakage current
Output leakage current
Input HIGH voltage
Input LOW voltage
Output LOW voltage
Min.
Limits
Typ. Max.
1
100
VCC x 0.7
-0.5
1
10
10
VCC + 0.5
VCC x 0.1
0.4
Unit
mA
µA
µA
µA
µA
V
V
V
Test Conditions
fSCL = 400kHz, SDA = Open,
Other Inputs = VSS
fSCL = 400kHz, SDA = Open,
Other Inputs = VSS
SCL = SDA = VCC, Addr. = VSS
VIN = VSS to VCC
VOUT = VSS to VCC
IOL = 3mA
Notes: (1) Absolute linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used as a
potentiometer.
(2) Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a
potentiometer. It is a measure of the error in step size.
(3) MI = RTOT/63 or (RH - RL)/63, single pot
ENDURANCE AND DATA RETENTION
Parameter
Minimum endurance
Data retention
Min.
100,000
100
Unit
Data changes per bit per register
Years
CAPACITANCE
Symbol
CI/O(4)
CIN(4)
Test
Input/output capacitance (SDA)
Input capacitance (A0, A1, A2, A3, and SCL)
Max.
8
6
Unit
pF
pF
Test Conditions
VI/O = 0V
VIN = 0V
POWER-UP TIMING
Symbol
tPUR(5)
tPUW(5)
tRVCC(6)
Parameter
Power-up to initiation of read operation
Power-up to initiation of write operation
VCC Power up ramp rate
Min.
0.2
Typ.
Max.
1
5
50
Unit
ms
ms
V/msec
Power Up Requirements (Power up sequencing can affect correct recall of the wiper registers)
The preferred power-on sequence is as follows: First VCC, then V+ and V-, and then the potentiometer pins, RH, RL,
and RW. Voltage should not be applied to the potentiometer pins before V+ or V- is applied. The VCC ramp rate
specification should be met, and any glitches or slope changes in the VCC line should be held to <100mV if possible.
If VCC powers down, it should be held below 0.1V for more than 1 second before powering up again in order for
proper wiper register recall. Also, VCC should not reverse polarity by more than 0.5V. Recall of wiper position will not
be complete until VCC, V+ and V- reach their final value.
Notes: (4) This parameter is periodically sampled and not 100% tested
(5) tPUR and tPUW are the delays required from the time the third (last) power supply (VCC, V+ or V-) is stable until the specific
instruction can be issued. These parameters are periodically sampled and not 100% tested.
(6) This is a tested or guaranteed parameter and should only be used as a guidance.
12 FN8194.3
October 12, 2006

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