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PDF X9259 Data sheet ( Hoja de datos )
| Número de pieza | X9259 | |
| Descripción | Quad Digitally-Controlled Potentiometers | |
| Fabricantes | Intersil Corporation | |
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DATASHEET
Single Supply/Low Power/256-Tap/2-Wire Bus Quad
Digitally-Controlled (XDCP™) Potentiometers
X9259
The X9259 integrates four digitally controlled potentiometers
(XDCP) on a monolithic CMOS integrated circuit.
The digitally controlled potentiometers are implemented with
a combination of resistor elements and CMOS switches. The
position of the wipers are controlled by the user through the
2-wire bus interface. Each potentiometer has associated with
it a volatile Wiper Counter Register (WCR) and four nonvolatile
Data Registers that can be directly written to and read by the
user. The content of the WCR controls the position of the wiper.
At power-up, the device recalls the content of the default Data
Registers of each DCP (DR00, DR10, DR20, and DR30) to the
corresponding WCR.
The XDCP can be used as a three-terminal potentiometer or as
a two-terminal variable resistor in a wide variety of
applications including control, parameter adjustments, and
signal processing.
Features
• Four separate potentiometers in one package
• 256 resistor taps–0.4% resolution
• 2-wire serial interface for write, read, and
transfer operations of the potentiometer
• Wiper resistance: 100Ω typical at VCC = 5V
• 4 nonvolatile data registers for each potentiometer
• Nonvolatile storage of multiple wiper positions
• Standby current <5µA max
• VCC: 2.7V to 5.5V operation
• 50kΩ version of total resistance
• Endurance: 100,000 data changes per bit per register
• 100 year data retention
• Single supply version of X9258
• 24 Ld SOIC, 24 Ld TSSOP
• Low power CMOS
• Pb-Free (RoHS compliant)
Functional Diagram
VCC
RH0
RH1
RH2
RH3
A3
A2
A1
A0
SDA
SCL
2-WIRE
INTERFACE
POWER UP,
INTERFACE
CONTROL
AND
STATUS
WCR0
DR00
DR01
DR02
DR03
DCP0
WCR1
DR10
DR11
DR12
DR13
DCP1
WCR2
DR20
DR21
DR22
DR23
DCP2
WCR3
DR30
DR31
DR32
DR33
DCP3
VSS
WP
RW0 RL0
RW1 RL1
RW2 RL2
RW3 RL3
December 12, 2014
FN8169.6
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 |Copyright Intersil Americas LLC 2005-2007, 2014. All Rights Reserved
Intersil (and design) and XDCP are trademarks owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
1 page  
X9259
Principles of Operation
The X9259 is an integrated circuit incorporating four DCPs and
their associated registers and counters, and the serial interface
providing direct communication between a host and the
potentiometers.
transferring the contents of one of four associated data registers
via the XFR Data Register instruction (parallel load); it can be
modified one step at a time by the Increment/Decrement
instruction (see “Instructions” section on page 8 for more
details). Finally, it is loaded with the contents of its data register
zero (DR#0) upon power-up, (see Figure 1 on page 4).
DCP Description
Each DCP is implemented with a combination of resistor
elements and CMOS switches. The physical ends of each DCP are
equivalent to the fixed terminals of a mechanical potentiometer
(RH and RL pins). The RW pin is an intermediate node, equivalent
to the wiper terminal of a mechanical potentiometer.
The position of the wiper terminal within the DCP is controlled by
an 8-bit volatile Wiper Counter Register (WCR).
Power Up and Down Recommendations
There are no restrictions on the power-up or power-down
conditions of VCC and the voltages applied to the potentiometer
pins provided that VCC is always more positive than or equal to
VH, VL, and VW, i.e., VCC VH, VL, VW. The VCC ramp rate
specification is always in effect.
Wiper Counter Register (WCR)
The X9259 contains four Wiper Counter Registers, one for each
potentiometer. The Wiper Counter Register can be envisioned as
a 8-bit parallel and serial load counter with its outputs decoded
to select one of 256 wiper positions along its resistor array. The
contents of the WCR can be altered in four ways: it may be
written directly by the host via the Write Wiper Counter Register
instruction (serial load); it may be written indirectly by
The Wiper Counter Register is a volatile register; that is, its
contents are lost when the X9259 is powered-down. Although the
register is automatically loaded with the value in DR#0 upon
power-up, this may be different from the value present at
power-down. Power-up guidelines are recommended to ensure
proper loadings of the DR#0 value into the WCR# (see AN162).
Data Registers (DR)
Each of the four DCPs has four 8-bit nonvolatile Data Registers.
These can be read or written directly by the host. Data can also
be transferred between any of the four data registers and the
associated Wiper Counter Register. All operations changing data
in one of the data registers is a nonvolatile operation and takes a
maximum of 10ms.
If the application does not require storage of multiple settings for
the potentiometer, the Data Registers can be used as regular
memory locations for system parameters or user preference
data.
Bit [7:0] are used to store one of the 256 wiper positions
(0 ~ 255).
TABLE 1. WIPER COUNTER REGISTER, WCR (8-BIT), WCR[7:0]: USED TO STORE THE CURRENT WIPER POSITION (VOLATILE).
WCR7
WCR6
WCR5
WCR4
WCR3
WCR2
WCR1
WCR0
(MSB)
(LSB)
BIT 7
(MSB)
TABLE 2. DATA REGISTER, DR (8-BIT), BIT [7:0]: USED TO STORE WIPER POSITIONS OR DATA (NONVOLATILE).
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
(LSB)
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5
FN8169.6
December 12, 2014
5 Page 
X9259
Transfer Wiper Counter Register (WCR) to Data Register (DR)
S
T
A
R
T
DEVICE TYPE
IDENTIFIER
0101
DEVICE
ADDRESSES
A3 A2 A1 A0
S
A
C
K
INSTRUCTION
OPCODE
1110
DR/WCR
ADDRESSES
RB RA P1 P0
S
A
C
K
S
T
O
P
HIGH-VOLTAGE
WRITE CYCLE
Transfer Data Register (DR) to Wiper Counter Register (WCR)
S
T
A
R
T
DEVICE TYPE
IDENTIFIER
0101
DEVICE
ADDRESSES
S
A
INSTRUCTION
OPCODE
C
A3 A2 A1 A0 K 1 1 0 1
DR/WCR
ADDRESSES
RB RA P1 P0
SS
AT
CO
KP
Increment/Decrement Wiper Counter Register (WCR)
S
T
A
R
T
DEVICE TYPE
IDENTIFIER
0101
DEVICE
ADDRESSES
A3 A2 A1 A0
S
A
C
K
INSTRUCTION
OPCODE
0010
DR/WCR
ADDRESSES
0 0 P1 P0
S
A
INCREMENT/DECREMENT
(SENT BY MASTER ON SDA)
C
K I/D I/D . . . . I/D I/D
NOTES:
5. “MACK”/”SACK”: stands for the acknowledge sent by the Master/Slave.
6. “A3 ~ A0”: stands for the device addresses sent by the master.
7. “X”: indicates that it is a “0” for testing purpose but physically it is a “don’t care” condition.
8. “I”: stands for the increment operation, SDA held high during active SCL phase (high).
9. “D”: stands for the decrement operation, SDA held low during active SCL phase (high).
S
T
O
P
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FN8169.6
December 12, 2014
11 Page | ||
| Páginas | Total 21 Páginas | |
| PDF Descargar | [ Datasheet X9259.PDF ] | |
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