PDF LMX2487E Data sheet ( Hoja de datos )

Número de pieza	LMX2487E
Descripción	High Performance Delta-Sigma Low Power Dual PLLatinum Frequency Synthesizers
Fabricantes	National Semiconductor
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No Preview Available ! May 2007 LMX2487E 7.5 GHz High Performance Delta-Sigma Low Power Dual PLLatinum™ Frequency Synthesizers with 3.0 GHz Integer PLL General Description ■ WLAN Standards The LMX2487E is a low power, high performance delta-sigma fractional-N PLL with an auxiliary integer-N PLL. It is fabricat- ed using National Semiconductor’s advanced process. With delta-sigma architecture, fractional spurs at lower offset frequencies are pushed to higher frequencies outside the loop bandwidth. The ability to push close in spur and phase noise energy to higher frequencies is a direct function of the mod- ulator order. Unlike analog compensation, the digital feed- back technique used in the LMX2487E is highly resistant to changes in temperature and variations in wafer processing. The LMX2487E delta-sigma modulator is programmable up to fourth order, which allows the designer to select the opti- mum modulator order to fit the phase noise, spur, and lock time requirements of the system. Serial data for programming the LMX2487E is transferred via a three line high speed (20 MHz) MICROWIRE interface. The LMX2487E offers fine frequency resolution, low spurs, fast programming speed, and a single word write to change the frequency. This makes it ideal for direct digital modulation applications, where the N counter is directly modulated with information. The LMX2487E is available in a 24 lead 4.0 X 4.0 X 0.8 mm LLP package. Applications ■ Cellular phones and base stations ■ Direct digital modulation applications ■ Satellite and cable TV tuners Features Quadruple Modulus Prescalers for Lower Divide Ratios ■ RF PLL: 16/17/20/21 or 32/33/36/37 ■ IF PLL: 8/9 or 16/17 Advanced Delta Sigma Fractional Compensation ■ 12 bit or 22 bit selectable fractional modulus ■ Up to 4th order programmable delta-sigma modulator Features for Improved Lock Times and Programming ■ Fastlock / Cycle slip reduction ■ Integrated time-out counter ■ Single word write to change frequencies with Fastlock Wide Operating Range ■ LMX2487E RF PLL: 3.0 GHz to 7.5 GHz Useful Features ■ Digital lock detect output ■ Hardware and software power-down control ■ On-chip crystal reference frequency doubler. ■ RF phase comparison frequency up to 50 MHz ■ 2.5 to 3.6 volt operation with ICC = 8.5 mA at 3.0 V Functional Block Diagram PLLatinum™ is a trademark of National Semiconductor Corporation. © 2007 National Semiconductor Corporation 300139 30013901 www.national.com 1 page Symbol Parameter Conditions PHASE NOISE RF_CPG = 0 LF1HzRF RF Synthesizer RF_CPG = 1 Normalized Phase Noise RF_CPG = 3 Contribution(Note 6) RF_CPG = 7 RF_CPG = 15 LF1HzIF IF Synthesizer Normalized Phase Noise Contribution DIGITAL INTERFACE (DATA, CLK, LE, ENOSC, CE, Ftest/LD, FLoutRF) VIH High-Level Input Voltage VIL Low-Level Input Voltage IIH High-Level Input Current VIH = VCC IIL Low-Level Input Current VIL = 0 V VOH High-Level Output Voltage IOH = -500 µA VOL Low-Level Output Voltage IOL = 500 µA MICROWIRE INTERFACE TIMING tCS Data to Clock Set Up Time See MICROWIRE Input Timing tCH tCWH tCWL tES Data to Clock Hold Time See MICROWIRE Input Timing Clock Pulse Width High See MICROWIRE Input Timing Clock Pulse Width Low See MICROWIRE Input Timing Clock to Load Enable Set Up Time See MICROWIRE Input Timing tEW Load Enable Pulse Width See MICROWIRE Input Timing Value Min Typ -202 -204 -206 -210 -210 -209 Units Max dBc/Hz dBc/Hz 1.6 -1.0 -1.0 VCC-0.4 VCC V 0.4 V 1.0 µA 1.0 µA V 0.4 V 25 ns 8 ns 25 ns 25 ns 25 ns 25 ns Note 3: For Phase Detector Frequencies above 20 MHz, Cycle Slip Reduction (CSR) may be required. Legal divide ratios are also required. Note 4: Refer to table in Section 2.4.2 RF_CPG -- RF PLL Charge Pump Gain for complete listing of charge pump currents. Note 5: In order to measure the in-band spur, the fractional word is chosen such that when reduced to lowest terms, the fractional numerator is one. The spur offset frequency is chosen to be the comparison frequency divided by the reduced fractional denominator. The loop bandwidth must be sufficiently wide to negate the impact of the loop filter. Measurement conditions are: Spur Offset Frequency = 10 kHz, Loop Bandwidth = 100 kHz, Fraction = 1/2000, Comparison Frequency = 20 MHz, RF_CPG = 7, DITH = 0, VCO Frequency = 3 GHz, and a 4th Order Modulator (FM = 0). These are relatively consistent over tuning range. Note 6: Normalized Phase Noise Contribution is defined as: LN(f) = L(f) – 20log(N) – 10log(fCOMP) where L(f) is defined as the single side band phase noise measured at an offset frequency, f, in a 1 Hz Bandwidth. The offset frequency, f, must be chosen sufficiently smaller than the PLL loop bandwidth, yet large enough to avoid substantial phase noise contribution from the reference source. Measurement conditions are: Offset Frequency = 11 kHz, Loop Bandwidth = 100 kHz for RF_CPG = 7, Fraction = 1/2000, Comparison Frequency = 20 MHz, FM = 0, DITH = 0, VCO Frequency = 3 GHz. MICROWIRE INPUT TIMING DIAGRAM 30013975 5 www.national.com 5 Page Typical Performance Characteristic : FinIF Input Impedance (Note 7) Frequency (MHz) 100 150 200 250 300 400 500 600 700 800 900 1000 1200 1400 1600 1800 2000 2200 2300 2400 2600 2800 3000 FinIF Input Impedance Real (Ohms) 508 456 420 403 370 344 207 274 242 242 214 171 137 112 91 76 62 51 46 42 37 29 25 30013954 Imaginary (Ohms) -233 -215 -206 -205 -207 -215 -223 -225 -225 -225 -222 -208 -191 -176 -158 -139 -122 -105 -96 -88 -74 -63 -54 11 www.national.com 11 Page

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