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PDF X40431 Data sheet ( Hoja de datos )
| Número de pieza | X40431 | |
| Descripción | (X40430 / X40431) Triple Voltage Monitor | |
| Fabricantes | Xicor | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de X40431 (archivo pdf) en la parte inferior de esta página. Total 24 Páginas | ||
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Preliminary Information
4kbit EEPROM
X40430/X40431
Triple Voltage Monitor with Integrated CPU Supervisor
FEATURES
• Triple voltage detection and reset assertion
—Three standard reset threshold settings
(4.6V/2.9V/1.7V, 4.4V/2.6V/1.7V,
2.9V/1.7V/2.4V)
—Adjust low voltage reset threshold voltages
using special programming sequence
—Reset signal valid to VCC = 1V
—Monitor three voltages or detect power fail
• Fault detection register
• Selectable power on reset timeout
• Selectable watchdog timer interval
• Debounced manual reset input
• Low power CMOS
—30µA typical standby current, watchdog on
—10µA typical standby current, watchdog off
• 4Kbits of EEPROM
—16 byte page write mode
—Self-timed write cycle
www.DataSheet4U.com — 5ms write cycle time (typical)
• Built-in inadvertent write protection
—Power-up/power-down protection circuitry
—Block lock protect 0, 1/4, 1/2, all of EEPROM
• 400kHz I2C interface
• 2.4V to 5.5V power supply operation
• Available packages
—14-lead SOIC, TSSOP
BLOCK DIAGRAM
DESCRIPTION
The X40430/31 combines power-on reset control,
watchdog timer, supply voltage supervision, secondary
and third voltage supervision, manual reset, and Block
Lock™ protect serial EEPROM in one package. This
combination lowers system cost, reduces board space
requirements, and increases reliability.
Applying voltage to VCC activates the power on reset
circuit which holds RESET/RESET active for a period of
time. This allows the power supply and system oscillator
to stabilize before the processor can execute code.
Low VCC detection circuitry protects the user’s system
from low voltage conditions, resetting the system when
VCC falls below the minimum VTRIP1 point. RESET/
RESET is active until VCC returns to proper operating
level and stabilizes. A second and third voltage monitor
circuit tracks the unregulated supply to provide a
power fail warning or monitors different power supply
voltage. Three common low voltage combinations are
available, however, Xicor’s unique circuits allows the
threshold for either voltage monitor to be repro-
grammed to meet special needs or to fine-tune the
threshold for applications requiring higher precision.
V3MON
V2MON
V3 Monitor
Logic
+
VTRIP3
-
V2 Monitor
Logic
+
VTRIP2
-
V3FAIL
V2FAIL
SDA
WP
SCL
VCC
(V1MON)
Data
Register
Command
Decode Test
& Control
Logic
REV 1.2.3 11/28/00
Fault Detection
Register
Status
Register
EEPROM
Array
VCCLoMgoicnitor
+
VTRIP1
-
www.xicor.com
Watchdog
and
Reset Logic
WDO
MR
Power on,
Manual Reset
Low Voltage
Reset
Generation
RESET
X40430
RESET
X40431
LOWLINE
Characteristics subject to change without notice. 1 of 24
1 page  
X40430/X40431 – Preliminary Information
Figure 3. VTRIPX Set/Reset Conditions
VTRIPX
(X = 1, 2, 3)
VCC/V2MON/V3MON
WDO
SCL
0
70
VP
70
7
SDA
A0h
00h tWC
WATCHDOG TIMER
The Watchdog Timer circuit monitors the microproces-
sor activity by monitoring the SDA and SCL pins. The
microprocessor must toggle the SDA pin HIGH to LOW
periodically, while SCL also toggles from HIGH to LOW
(this is a start bit) followed by a stop condition prior to
the expiration of the watchdog time out period to pre-
vent a WDO signal going active. The state of two non-
volatile control bits in the Status Register determine
the watchdog timer period. The microprocessor can
change these watchdog bits by writing to the X40430/
31 control register (also refer to page 20).
Figure 4. Watchdog Restart
.6µs
1.3µs
SCL
SDA
Timer Start
V1, V2 AND V3 THRESHOLD PROGRAM
PROCEDURE
The X40430 is shipped with standard V1, V2 and V3
threshold (VTRIP1, VTRIP2, VTRIP3) voltages. These
values will not change over normal operating and stor-
age conditions. However, in applications where the
standard thresholds are not exactly right, or if higher
precision is needed in the threshold value, the X40430
trip points may be adjusted. The procedure is described
below, and uses the application of a high voltage control
signal.
Setting a VTRIPx Voltage (x=1, 2, 3)
There are two procedures used to set the threshold
voltages (VTRIPx), depending if the threshold voltage to
be stored is higher or lower than the present value. For
example, if the present VTRIPx is 2.9 V and the new
VTRIPx is 3.2 V, the new voltage can be stored directly
into the VTRIPx cell. If however, the new setting is to be
lower than the present setting, then it is necessary to
“reset” the VTRIPx voltage before setting the new value.
Setting a Higher VTRIPx Voltage (x=1, 2, 3)
To set a VTRIPx threshold to a new voltage which is
higher than the present threshold, the user must apply
the desired VTRIPx threshold voltage to the corre-
sponding input pin (Vcc(V1MON), V2MON or V3MON).
The Vcc(V1MON), V2MON and V3MON must be tied
together during this sequence. Then, a programming
voltage (Vp) must be applied to the WDO pin before a
START condition is set up on SDA. Next, issue on the
SDA pin the Slave Address A0h, followed by the Byte
Address 01h for VTRIP1, 09h for VTRIP2, and 0Dh for
VTRIP3, and a 00h Data Byte in order to program
VTRIPx. The STOP bit following a valid write operation
initiates the programming sequence. Pin WDO must
then be brought LOW to complete the operation
REV 1.2.3 11/28/00
www.xicor.com
Characteristics subject to change without notice. 5 of 24
5 Page 
X40430/X40431 – Preliminary Information
Figure 10. Byte Write Sequence
Signals from
the Master
SDA Bus
Signals from
the Slave
S
t
a
r
Slave
Address
t
Byte
Address
0
AA
CC
KK
Data
S
t
o
p
A
C
K
Page Write
The device is capable of a page write operation. It is
initiated in the same manner as the byte write opera-
tion; but instead of terminating the write cycle after the
first data byte is transferred, the master can transmit
an unlimited number of 8-bit bytes. After the receipt of
each byte, the device will respond with an acknowl-
edge, and the address is internally incremented by
one. The page address remains constant. When the
counter reaches the end of the page, it “rolls over” and
goes back to ‘0’ on the same page.
This means that the master can write 16 bytes to the
page starting at any location on that page. If the mas-
ter begins writing at location 10, and loads 12 bytes,
then the first 6 bytes are written to locations 10 through
15, and the last 6 bytes are written to locations 0
through 5. Afterwards, the address counter would point
to location 6 of the page that was just written. If the
master supplies more than 16 bytes of data, then new
data overwrites the previous data, one byte at a time.
Figure 11. Page Write Operation
Signals from
the Master
SDA Bus
S
t
a
r
t
Signals from
the Slave
Slave
Address
Byte
Address
0
A
C
K
A
C
K
Data
(1)
(1 ≤ n ≤ 16)
Data
(n)
A
C
K
S
t
o
p
A
C
K
Figure 12. Writing 12 bytes to a 16-byte page starting at location 10.
7 Bytes
5 Bytes
address
=6
address pointer
ends here
Addr = 7
address
10
address
n-1
The master terminates the Data Byte loading by issuing
a stop condition, which causes the device to begin the
nonvolatile write cycle. As with the byte write operation,
all inputs are disabled until completion of the internal
write cycle. See Figure 11 for the address, acknowl-
edge, and data transfer sequence.
REV 1.2.3 11/28/00
www.xicor.com
Characteristics subject to change without notice. 11 of 24
11 Page | ||
| Páginas | Total 24 Páginas | |
| PDF Descargar | [ Datasheet X40431.PDF ] | |
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