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X4043 Schematic ( PDF Datasheet ) - Intersil Corporation

Teilenummer X4043
Beschreibung (X4043 / X4045) CPU Supervisor
Hersteller Intersil Corporation
Logo Intersil Corporation Logo 




Gesamt 24 Seiten
X4043 Datasheet, Funktion
®
Data Sheet
September 30, 2005
X4043, X4045
4k, 512 x 8 Bit
FN8118.1
CPU Supervisor with 4kbit EEPROM
FEATURES
• Selectable watchdog timer
• Low VCC detection and reset assertion
—Five standard reset threshold voltages
—Adjust low VCC reset threshold voltage using
special programming sequence
—Reset signal valid to VCC = 1V
• Low power CMOS
—<20µA max standby current, watchdog on
—<1µA standby current, watchdog OFF
—3mA active current
• 4kbits of EEPROM
—16-byte page write mode
—Self-timed write cycle
—5ms write cycle time (typical)
• Built-in inadvertent write protection
—Power-up/power-down protection circuitry
—Protect 0, 1/4, 1/2, all or 16, 32, 64 or 128 bytes
of EEPROM array with Block Lockprotection
• 400kHz 2-wire interface
• 2.7V to 5.5V power supply operation
www.DataSheet4U.com Available packages
—8 Ld SOIC
—8 Ld MSOP
—8 Ld PDIP
• Pb-free plus anneal available (RoHS compliant)
BLOCK DIAGRAM
DESCRIPTION
The X4043/45 combines four popular functions,
Power-on Reset Control, Watchdog Timer, Supply
Voltage Supervision, and Block Lock Protect Serial
EEPROM Memory in one package. This combination
lowers system cost, reduces board space require-
ments, and increases reliability.
Applying power to the device activates the power-on
reset circuit which holds RESET/RESET active for a
period of time. This allows the power supply and oscilla-
tor to stabilize before the processor can execute code.
The Watchdog Timer provides an independent protec-
tion mechanism for microcontrollers. When the micro-
controller fails to restart a timer within a selectable
time out interval, the device activates the
RESET/RESET signal. The user selects the interval
from three preset values. Once selected, the interval
does not change, even after cycling the power.
The device’s low VCC detection circuitry protects the
user’s system from low voltage conditions, resetting the
system when VCC falls below the minimum VCC trip
point. RESET/RESET is asserted until VCC returns to
proper operating level and stabilizes. Five industry stan-
dard VTRIP thresholds are available, however, Intersil’s
unique circuits allow the threshold to be reprogrammed
to meet custom requirements or to fine-tune the thresh-
old for applications requiring higher precision.
WP
SDA
SCL
VCC
Watchdog Transition
Detector
Data
Register
Command
Decode &
Control
Logic
VCC Threshold
Reset logic
Protect Logic
Status
Register
EEPROM Array
VTRIP
+
-
Watchdog
Timer Reset
Reset &
Watchdog
Timebase
Power-on and
Low Voltage
Reset
Generation
RESET (X4043)
RESET (X4045)
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2005. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.






X4043 Datasheet, Funktion
X4043, X4045
Setting a VTRIP Voltage
There are two procedures used to set the threshold
voltages (VTRIP), depending if the threshold voltage to
be stored is higher or lower than the present value. For
example, if the present VTRIP is 2.9 V and the new
VTRIP is 3.2 V, the new voltage can be stored directly
into the VTRIP cell. If however, the new setting is to be
lower than the present setting, then it is necessary to
“reset” the VTRIP voltage before setting the new value.
Setting a Higher VTRIP Voltage
To set a VTRIP threshold to a new voltage which is
higher than the present threshold, the user must apply
the desired VTRIP threshold voltage to the VCC. Then,
a programming voltage (Vp) must be applied to the
WP pin before a START condition is set up on SDA.
Next, issue on the SDA pin the Slave Address A0h,
followed by the Byte Address 01h for VTRIP and a 00h
Data Byte in order to program VTRIP . The STOP bit
following a valid write operation initiates the program-
ming sequence. WP pin must then be brought LOW to
complete the operation.
To check if the VTRIP has been set, first power-down
the device. Slowly ramp up VCC and observe when the
output, RESET (4043) or RESET (4045) switches. The
voltage at which this occurs is the VTRIP (actual) (see
Figure 2).
CASE A
Now if the desired VTRIP is greater than the VTRIP
(actual), then add the difference between VTRIP
(desired) - VTRIP (actual) to the original VTRIP desired.
This is your new VTRIP that should be applied to VCC
and the whole sequence should be repeated again
(see Figure 5).
CASE B
Now if the VTRIP (actual), is higher than the VTRIP
(desired), perform the reset sequence as described in
the next section. The new VTRIP voltage to be applied to
VCC will now be: VTRIP (desired) - (VTRIP (actual) - VTRIP
(desired)).
Note: This operation does not corrupt the memory
array.
Setting a Lower VTRIP Voltage
In order to set VTRIP to a lower voltage than the
present value, then VTRIP must first be “reset” accord-
ing to the procedure described below. Once VTRIP has
been “reset”, then VTRIP can be set to the desired volt-
age using the procedure described in “Setting a Higher
VTRIP Voltage”.
Resetting the VTRIP Voltage
To reset a VTRIP voltage, apply the programming volt-
age (Vp) to the WP pin before a START condition is
set up on SDA. Next, issue on the SDA pin the Slave
Address A0h followed by the Byte Address 03h fol-
lowed by 00h for the Data Byte in order to reset VTRIP.
The STOP bit following a valid write operation initiates
the programming sequence. Pin WP must then be
brought LOW to complete the operation.
After being reset, the value of VTRIP becomes a nomi-
nal value of 1.7V or lesser.
Note: This operation does not corrupt the memory
array.
6 FN8118.1
September 30, 2005

6 Page









X4043 pdf, datenblatt
X4043, X4045
Figure 10. Byte Write Sequence
S
Signals from
t
Slave
the Master a Address
r
t
SDA Bus
0
Byte
Address
Signals from
the Slave
AA
CC
KK
Data
S
t
o
p
A
C
K
Page Write
The device is capable of a page write operation. It is
initiated in the same manner as the byte write opera-
tion; but instead of terminating the write cycle after the
first data byte is transferred, the master can transmit
an unlimited number of 8-bit bytes. After the receipt of
each byte, the device will respond with an acknowl-
edge, and the address is internally incremented by
one. The page address remains constant. When the
counter reaches the end of the page, it “rolls over” and
goes back to ‘0’ on the same page. This means that
the master can write 16 bytes to the page starting at
any location on that page. If the master begins writing
at location 10, and loads 12 bytes, then the first 5
bytes are written to locations 10 through 15, and the
last 7 bytes are written to locations 0 through 6. After-
wards, the address counter would point to location 7 of
the page that was just written. If the master supplies
more than 16 bytes of data, then new data over-writes
the previous data, one byte at a time.
Figure 11. Page Write Operation
S
Signals from
the Master
t
a
r
Slave
Address
t
SDA Bus
0
Signals from
the Slave
A
C
K
Byte
Address
A
C
K
Data
(1)
(1 n 16)
Data
(n)
A
C
K
S
t
o
p
A
C
K
Figure 12. Writing 12-bytes to a 16-byte page starting at location 10
7 Bytes
Address
=6
Address Pointer
Ends Here
Addr = 7
The master terminates the data byte loading by issu-
ing a stop condition, which causes the device to begin
the nonvolatile write cycle. As with the byte write opera-
tion, all inputs are disabled until completion of the inter-
nal write cycle. See Figure 11 for the address,
acknowledge, and data transfer sequence.
5 Bytes
Address
10
Address
n-1
Stops and Write Modes
Stop conditions (that terminate write operations) must
be sent by the master after sending at least 1 full data
byte, plus the subsequent ACK signal. If a stop is
issued in the middle of a data byte, or before 1 full
data byte plus its associated ACK is sent, then the
device will reset itself without performing the write. The
contents of the array will not be effected.
12 FN8118.1
September 30, 2005

12 Page





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