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PDF X40421 Data sheet ( Hoja de datos )

Número de pieza X40421
Descripción (X40420 / X40421) Dual Voltage Monitor
Fabricantes Intersil Corporation 
Logotipo Intersil Corporation Logotipo



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No Preview Available ! X40421 Hoja de datos, Descripción, Manual

®
PRELIMINARY
Data Sheet
X40420, X40421
4kbit EEPROM
March 28, 2005
FN8117.0
Dual Voltage Monitor with Integrated CPU
Supervisor and System Battery Switch
FEATURES
• Dual voltage detection and reset assertion
—Three standard reset threshold settings
(4.6V/2.9V, 4.6V/2.6V, 2.9V/1.6V)
—VTRIP2 Programmable down to 0.9V
—Adjust low voltage reset threshold voltages
using special programming sequence
—Reset signal valid to VCC = 1V
—Monitor two voltages or detect power fail
• Battery Switch Backup
• VOUT: 5mA to 50mA from VCC; or 250µA from
VBATT
• Fault detection register
• Selectable power-on reset timeout
(0.05s, 0.2s, 0.4s, 0.8s)
• Selectable watchdog timer interval
(25ms, 200ms, 1.4s, off)
• Debounced manual reset input
• Low power CMOS
—25µA typical standby current, watchdog on
—6µA typical standby current, watchdog off
—1µA typical battery current in backup mode
www.DataSheet4U.com 4Kbits of EEPROM
—16 byte page write mode
—Self-timed write cycle
—5ms write cycle time (typical)
• Built-in inadvertent write protection
—Power-up/power-down protection circuitry
—Block lock protect 0 or 1/2, of EEPROM
• 400kHz 2-wire interface
• 2.7V to 5.5V power supply operation
• Available packages
—14-lead SOIC, TSSOP
• •Monitor Voltages: 5V to 1.6V
• Memory Security
• Battery Switch Backup
• VOUT 5mA to 50mA
APPLICATIONS
• Communications Equipment
—Routers, Hubs, Switches
—Disk arrays
• Industrial Systems
—Process Control
—Intelligent Instrumentation
• Computer Systems
—Desktop Computers
—Network Servers
X40420/21
Standard VTRIP1 Level Standard VTRIP2 Level
4.6V (+/-1%)
2.9V(+/-1.7%)
4.6V (+/-1%)
2.6V (+/-2%)
2.9V(+/-1.7%)
1.6V (+/-3%)
See “Ordering Information” for more details
For Custom Settings, call Intersil.
Suffix
-A
-B
-C
DESCRIPTION
The X40420/21 combines power-on reset control,
watchdog timer, supply voltage supervision, and sec-
ondary supervision, manual reset, and Block Lock
protect serial EEPROM in one package. This combi-
nation lowers system cost, reduces board space
requirements, and increases reliability.
Applying voltage to VCC activates the power-on reset
circuit which holds RESET/RESET active for a period of
time. This allows the power supply and system oscilla-
tor to stabilize before the processor can execute code.
BLOCK DIAGRAM
V2MON
V2 Monitor
Logic
VOUT
+
VTRIP2
-
V2FAIL
SDA
WP
SCL
VCC
(V1MON)
BATT-ON
VOUT
VBATT
Data
Register
Command
Decode Test
& Control
Logic
System
Battery
Switch
Fault Detection
Register
Status
Register
EEPROM
Array
VCCLMogoicnitor
VOUT
+
VTRIP1
-
Watchdog
and
Reset Logic
VOUT
Power-on,
Manual Reset
Low Voltage
Reset
Generation
WDO
MR
RESET
X40420
RESET
X40421
LOWLINE
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-352-6832 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2005. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.

1 page




X40421 pdf
X40420, X40421
Figure 3. VTRIPX Set/Reset Conditions
VTRIPX
(X = 1, 2)
VCC/V2MON
WDO
VP
SCL 0
70
70
7
SDA
A0h
Figure 4. Watchdog Restart
.6µs
SCL
1.3µs
SDA
Start
WDT Reset Stop
V1 AND V2 THRESHOLD PROGRAM PROCEDURE
(OPTIONAL)
The X40420/21 is shipped with standard V1 and V2
threshold (VTRIP1, VTRIP2) voltages. These values will not
change over normal operating and storage conditions.
However, in applications where the standard thresholds
are not exactly right, or if higher precision is needed in
the threshold value, the X40420 trip points may be
adjusted. The procedure is described below, and uses
the application of a high voltage control signal.
Setting a VTRIPx Voltage (x = 1, 2)
There are two procedures used to set the threshold volt-
ages (VTRIPx), depending if the threshold voltage to be
stored is higher or lower than the present value. For
example, if the present VTRIPx is 2.9 V and the new
VTRIPx is 3.2 V, the new voltage can be stored directly
into the VTRIPx cell. If however, the new setting is to be
lower than the present setting, then it is necessary to
“reset” the VTRIPx voltage before setting the new value.
Setting a Higher VTRIPx Voltage (x = 1, 2)
To set a VTRIPx threshold to a new voltage which is
higher than the present threshold, the user must apply
the desired VTRIPx threshold voltage to the
corresponding input pin (Vcc(V1MON) or V2MON).
Then, a program-ming voltage (Vp) must be applied to
the WDO pin before a START condition is set up on
SDA. Next, issue on the SDA pin the Slave Address A0h,
followed by the Byte Address 01h for VTRIP1, and 09h for
VTRIP2, and a 00h Data Byte in order to program VTRIPx.
00h tWC
The STOP bit following a valid write operation initiates
the programming sequence. Pin WDO must then be
brought LOW to complete the operation.
To check if the VTRIPX has been set, set VXMON to a
value slightly greater than VTRIPX (that was previously
set). Slowly ramp down VXMON and observe when the
corresponding outputs (LOWLINE and V2FAIL) switch.
The voltage at which this occurs is the VTRIPX (actual).
CASE A
Now if the desired VTRIPX is greater than the VTRIPX
(actual), then add the difference between VTRIPX
(desired) - VTRIPX (actual) to the original VTRIPX desired.
This is your new VTRIPX that should be applied to
VXMON and the whole sequence should be repeated
again (see Figure 5).
CASE B
Now if the VTRIPX (actual), is higher than the VTRIPX
(desired), perform the reset sequence as described in
the next section. The new VTRIPX voltage to be applied
to VXMON will now be: VTRIPX (desired) - (VTRIPX
(actual) - VTRIPX (desired)).
Note: 1. This operation does not corrupt the memory
array.
2. Set VCC = 5V, when VTRIP2 is being pro-
grammed
Setting a Lower VTRIPx Voltage (x = 1, 2)
In order to set VTRIPx to a lower voltage than the
present value, then VTRIPx must first be “reset” accord-
ing to the procedure described below. Once VTRIPx
has been “reset”, then VTRIPx can be set to the desired
voltage using the procedure described in “Setting a
Higher VTRIPx Voltage”.
5 March 28, 2005

5 Page





X40421 arduino
X40420, X40421
Figure 10. Byte Write Sequence
Signals from
the Master
SDA Bus
Signals from
the Slave
S
t
a
r
Slave
Address
t
Byte
Address
0
AA
CC
KK
Data
S
t
o
p
A
C
K
Page Write
The device is capable of a page write operation. It is
initiated in the same manner as the byte write opera-
tion; but instead of terminating the write cycle after the
first data byte is transferred, the master can transmit
an unlimited number of 8-bit bytes. After the receipt of
each byte, the device will respond with an acknowl-
edge, and the address is internally incremented by
one. The page address remains constant. When the
counter reaches the end of the page, it “rolls over” and
goes back to ‘0’ on the same page.
This means that the master can write 16 bytes to the
page starting at any location on that page. If the master
begins writing at location 10, and loads 12 bytes, then
the first 6 bytes are written to locations 10 through 15,
and the last 6 bytes are written to locations 0 through 5.
Afterwards, the address counter would point to location
6 of the page that was just written. If the master sup-
plies more than 16 bytes of data, then new data over-
writes the previous data, one byte at a time.
Figure 11. Page Write Operation
Signals from
the Master
SDA Bus
Signals from
the Slave
S
t
a
r
Slave
Address
t
101 00 0
A
C
K
Byte
Address
A
C
K
Data
(1)
(1 n 16)
Data
(n)
A
C
K
S
t
o
p
A
C
K
Figure 12. Writing 12 bytes to a 16-byte page starting at location 10.
6 Bytes
address
=5
address pointer
ends here
Addr = 6
The master terminates the Data Byte loading by issuing
a stop condition, which causes the device to begin the
nonvolatile write cycle. As with the byte write operation,
6 Bytes
address
10
address
n-1
all inputs are disabled until completion of the internal
write cycle. See Figure 11 for the address, acknowl-
edge, and data transfer sequence.
11 March 28, 2005

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