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X40034 Schematic ( PDF Datasheet ) - Intersil Corporation

Teilenummer X40034
Beschreibung (X40030 - X40035) Triple Voltage Monitor
Hersteller Intersil Corporation
Logo Intersil Corporation Logo 




Gesamt 24 Seiten
X40034 Datasheet, Funktion
®
PRELIMINARY
Data Sheet
X40030, X40031, X40034, X40035
May 25, 2006
FN8114.1
Triple Voltage Monitor with Integrated
CPU Supervisor
FEATURES
• Triple voltage detection and reset assertion
—Standard reset threshold settings
see selection table on page 5.
—Adjust low voltage reset threshold voltages
using special programming sequence
—Reset signal valid to VCC = 1V
—Monitor three seperate voltages
• Fault detection register
• Selectable power on reset timeout
(0.05s, 0.2s, 0.4s, 0.8s)
• Selectable watchdog timer interval
(25ms, 200ms, 1.4s or off)
• Debounced manual reset input
• Low power CMOS
—25µA typical standby current, watchdog on
—6µA typical standby current, watchdog off
• 400kHz 2-wire interface
• 2.7V to 5.5V power supply operation
• Available in 14 Ld SOIC, TSSOP packages
www.DataSheet4U.com Monitor voltages: 5V to 0.9V
• Independent core voltage monitor
• Pb-free plus anneal available (RoHS compliant)
APPLICATIONS
• Communication equipment
—Routers, hubs, switches
—Disk arrays, network storage
BLOCK DIAGRAM
• Industrial systems
—Process control
—Intelligent instrumentation
• Computer systems
— Computers
—Network servers
DESCRIPTION
The X40030, X40031, X40034, X40035 combine
power-on reset control, watchdog timer, supply voltage
supervision, second and third voltage supervision, and
manual reset, in one package. This combination lowers
system cost, reduces board space requirements, and
increases reliability.
Applying voltage to VCC activates the power on reset cir-
cuit which holds RESET/RESET active for a period of
time. This allows the power supply and system oscillator
to stabilize before the processor can execute code.
Low VCC detection circuitry protects the user’s system
from low voltage conditions, resetting the system when
VCC falls below the minimum VTRIP1 point.
RESET/RESET is active until VCC returns to proper
operating level and stabilizes. A second and third voltage
monitor circuit tracks the unregulated supply to provide a
power fail warning or monitors different power supply
voltage. Three common low voltage combinations are
available, however, Intersil’s unique circuits allows the
threshold for either voltage monitor to be reprogrammed
to meet specific system level requirements or to fine-tune
the threshold for applications requiring higher precision.
V3MON
V2MON
V3LMoognicitor
+
-
V2LMogoincitor
VTRIP3
+
-
VCC or
V2MON*
VTRIP2
V3FAIL
V2FAIL
SDA
WP
SCL
VCC
(V1MON)
Data
Register
Command
Decode Test
& Control
Logic
Fault Detection
Register
Status
Register
VCCLoMgoicnitor
+
VTRIP1
-
Watchdog
and
Reset Logic
Power on,
Manual Reset
Low Voltage
Reset
Generation
WDO
MR
RESET
X40030/34
RESET
X40031/35
LOWLINE
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2005-2006. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.






X40034 Datasheet, Funktion
X40030, X40031, X40034, X40035
PIN DESCRIPTION (Continued)
Pin Name
Function
7 VSS Ground
8
SDA
Serial Data. SDA is a bidirectional pin used to transfer data into and out of the device. It has an
open drain output and may be wire ORed with other open drain or open collector outputs. This pin
requires a pull up resistor and the input buffer is always active (not gated).
Watchdog Input. A HIGH to LOW transition on the SDA (while SCL is toggled from HIGH to LOW
and followed by a stop condition) restarts the Watchdog timer. The absence of this transition within
the watchdog time out period results in WDO going active.
9 SCL Serial Clock. The Serial Clock controls the serial bus timing for data input and output.
10 WP Write Protect. WP HIGH prevents writes to any location in the device (includung all the registers).
It has an internal pull down resistor. (>10Mtypical)
11 V3MON V3 Voltage Monitor Input. When the V3MON input is less than the VTRIP3 voltage, V3FAIL goes
LOW. This input can monitor an unregulated power supply with an external resistor divider or can
monitor a
not used.
third power supply with no external components. Connect
The V3MON comparator is supplied by the V3MON input.
V3MON
to
VSS
or
VCC
when
12 V3FAIL V3 Voltage Fail Output. This open drain output goes LOW when V3MON is less than VTRIP3 and
goes HIGH when V3MON exceeds VTRIP3. There is no power up reset delay circuitry on this pin.
13 WDO WDO Output. WDO is an active LOW, open drain output which goes active whenever the watch-
dog timer goes active.
14 VCC Supply Voltage.
PRINCIPLES OF OPERATION
Power On Reset
Applying power to the X40030, X40031, X40034,
X40035 activates a Power On Reset Circuit that pulls
the RESET/RESET pins active. This signal provides
several benefits.
– It prevents the system microprocessor from starting
to operate with insufficient voltage.
– It prevents the processor from operating prior to sta-
bilization of the oscillator.
– It allows time for an FPGA to download its configura-
tion prior to initialization of the circuit.
– It prevents communication to the EEPROM, greatly
reducing the likelihood of data corruption on power up.
When VCC exceeds the device VTRIP1 threshold value
for tPURST (selectable) the circuit releases the RESET
(X40031, X40035) and RESET (X40030, X40034) pin
allowing the system to begin operation.
Figure 1. Connecting a Manual Reset Push-Button
X40030/34
VCC
System
Reset
RESET
MR
Manual
Reset
Manual Reset
By connecting a push-button directly from MR to
ground, the designer adds manual system reset capa-
bility. The MR pin is LOW while the push-button is
closed and RESET/RESET pin remains HIGH/LOW
until the push-button is released and for tPURST there-
after.
Low Voltage VCC (V1 Monitoring)
During operation, the X40030, X40031, X40034,
X40035 monitors the VCC level and asserts
RESET/RESET if supply voltage falls below a preset
minimum VTRIP1. The RESET signal prevents the
microprocessor from operating in a power fail or
brownout condition. The RESET/RESET signal
remains active until the voltage drops below 1V. It also
remains active until VCC returns and exceeds VTRIP1
for tPURST.
Low Voltage V2 Monitoring
The X40030 also monitors a second voltage level and
asserts V2FAIL if the voltage falls below a preset mini-
mum VTRIP2. The V2FAIL signal is either ORed with
RESET to prevent the microprocessor from operating
in a power fail or brownout condition or used to inter-
rupt the microprocessor with notification of an impend-
ing power failure.
For the X40030 and X40031 the V2FAIL signal
remains active until the V2MON drops below 1V
(V2MON falling). It also remains active until V2MON
6 FN8114.1
May 25, 2006

6 Page









X40034 pdf, datenblatt
X40030, X40031, X40034, X40035
Figure 7. Valid Data Changes on the SDA Bus
SCL
SDA
Data Stable
Data Change
Data Stable
At power-up, the FDR is defaulted to all “0”. The sys-
tem needs to initialize this register to all “1” before the
actual monitoring can take place. In the event of any
one of the monitored sources fail. The corresponding
bit in the register will change from a “1” to a “0” to indi-
cate the failure. At this moment, the system should
perform a read to the register and note the cause of
the reset. After reading the register the system should
reset the register back to all “1” again. The state of the
FDR can be read at any time by performing a random
read at address 0FFh, using the special preamble.
The FDR can be read by performing a random read at
0FFh address of the register at any time. Only one
byte of data is read by the register read operation.
MRF: Manual Reset Fail Bit (Volatile)
The MRF bit will be set to “0” when Manual Reset
input goes active.
WDF: Watchdog Timer Fail Bit (Volatile)
The WDF bit will be set to “0” when the WDO goes
active.
LV1F: Low VCC Reset Fail Bit (Volatile)
The LV1F bit will be set to “0” when VCC (V1MON)
falls below VTRIP1.
LV2F: Low V2MON Reset Fail Bit (Volatile)
The LV2F bit will be set to “0” when V2MON falls
below VTRIP2.
LV3F: Low V3MON Reset Fail Bit (Volatile)
The LV3F bit will be set to “0” when the V3MON falls
below VTRIP3.
SERIAL INTERFACE
Interface Conventions
The device supports a bidirectional bus oriented proto-
col. The protocol defines any device that sends data
onto the bus as a transmitter, and the receiving device
as the receiver. The device controlling the transfer is
called the master and the device being controlled is
called the slave. The master always initiates data
transfers, and provides the clock for both transmit and
receive operations. Therefore, the devices in this fam-
ily operate as slaves in all applications.
Serial Clock and Data
Data states on the SDA line can change only during
SCL LOW. SDA state changes during SCL HIGH are
reserved for indicating start and stop conditions. See
Figure 7.
Serial Start Condition
All commands are preceded by the start condition,
which is a HIGH to LOW transition of SDA when SCL
is HIGH. The device continuously monitors the SDA
and SCL lines for the start condition and will not
respond to any command until this condition has been
met. See Figure 8.
Serial Stop Condition
All communications must be terminated by a stop con-
dition, which is a LOW to HIGH transition of SDA when
SCL is HIGH. The stop condition is also used to place
the device into the Standby power mode after a read
sequence. A stop condition can only be issued after the
transmitting device has released the bus. See Figure 8.
12 FN8114.1
May 25, 2006

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