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ISL12025 Schematic ( PDF Datasheet ) - Intersil Corporation

Teilenummer ISL12025
Beschreibung Real-Time Clock/Calendar
Hersteller Intersil Corporation
Logo Intersil Corporation Logo 




Gesamt 27 Seiten
ISL12025 Datasheet, Funktion
®
Data Sheet
New Features
October 18, 2006
ISL12025
FN6371.1
Real-Time Clock/Calendar with EEPROM
The ISL12025 device is a low power real-time clock with
timing and crystal compensation, clock/calender, 64-bit
unique ID, power-fail indicator, two periodic or polled alarms,
intelligent battery backup switching, CPU Supervisor and
integrated 512 x 8-bit EEPROM, in a 16 Bytes per page
format.
The oscillator uses an external, low-cost 32.768kHz crystal.
The real-time clock tracks time with separate registers for
hours, minutes, and seconds. The device has calendar
registers for date, month, year and day of the week. The
calendar is accurate through 2099, with automatic leap year
correction.
Ordering Information
PART
TEMP.
PKG.
NUMBER PART VRESET RANGE PACKAGE DWG.
(Note) MARKING VOLTAGE (°C) (Pb-Free) #
ISL12025IBZ 12025IBZ 2.63V -40 to +85 8 Ld SOIC M8.15
ISL12025IVZ 2025IVZ
2.63V -40 to +85 8 Ld TSSOP M8.173
NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100% matte
www.DataSheet4U.cotmin plate termination finish, which are RoHS compliant and compatible
with both SnPb and Pb-free soldering operations. Intersil Pb-free
products are MSL classified at Pb-free peak reflow temperatures that
meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
Add “-T” suffix for tape and reel.
Pinouts
X1
X2
RESET
GND
ISL12025
(8 LD SOIC)
TOP VIEW
18
27
36
45
VDD
VBAT
SCL
SDA
VBAT
VDD
X1
X2
ISL12025
(8 LD TSSOP)
TOP VIEW
18
27
36
45
SCL
SDA
GND
RESET
Features
• Real-Time Clock/Calendar
- Tracks Time in Hours, Minutes, and Seconds
- Day of the Week, Day, Month, and Year
• 64-bit Unique ID
• Two Non-Volatile Alarms
- Settable on the Second, Minute, Hour, Day of the Week,
Day, or Month
- Repeat Mode (periodic interrupts)
• Automatic Backup to Battery or SuperCap
• On-Chip Oscillator Compensation
- Internal Feedback Resistor and Compensation
Capacitors
- 64 Position Digitally Controlled Trim Capacitor
- 6 Digital Frequency Adjustment Settings to ±30ppm
• 512 x 8 Bits of EEPROM
- 16-Bytes Page Write Mode (32 total pages)
- 8 Modes of Block Lock™ Protection
- Single Byte Write Capability
• High Reliability
- Data Retention: 50 years
- Endurance: 2,000,000 Cycles Per Byte
• I2C* Interface
- 400kHz Data Transfer Rate
• 800nA Battery Supply Current
• Package Options
- 8 Ld SOIC and 8 Ld TSSOP Packages
• Pb-Free Plus Anneal Available (RoHS Compliant)
Applications
• Utility Meters
• Audio/Video Components
• Modems
• Network Routers, Hubs, Switches, Bridges
• Cellular Infrastructure Equipment
• Fixed Broadband Wireless Equipment
• Pagers/PDA
• POS Equipment
• Test Meters/Fixtures
• Office Automation (Copiers, Fax)
• Home Appliances
• Computer Products
• Other Industrial/Medical/Automotive
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
*I2C is a Trademark of Philips. Copyright Intersil Americas Inc. 2006. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.






ISL12025 Datasheet, Funktion
Timing Diagrams
SCL
tSU:STA
SDA
(INPUT TIMING)
SDA
(OUTPUT TIMING)
ISL12025
tF tHIGH
tSU:DAT
tHD:STA
tLOW
tR
tHD:DAT
tAA tDH
FIGURE 1. BUS TIMING
tHD:STO
tSU:STO
tBUF
SCL
SDA
8TH BIT OF LAST BYTE
ACK
STOP
CONDITION
FIGURE 2. WRITE CYCLE TIMING
tWC
START
CONDITION
SCL
SDA
tRSP
tRSP<tWDO
tRSP>tWDO
tRST
tRSP>tWDO
tRST
RESET
START
STOP START
NOTE: ALL INPUTS ARE IGNORED DURING THE ACTIVE RESET PERIOD (tRST).
FIGURE 3. WATCHDOG TIMING
VRESET
VDD
tPURST
RESET
tR
6
tRPD
tPURST
FIGURE 4. RESET TIMING
tF
VRVALID
FN6371.1
October 18, 2006

6 Page









ISL12025 pdf, datenblatt
ISL12025
Alarm Registers (Non-Volatile)
Alarm0 and Alarm1
The alarm register bytes are set up identical to the RTC
register bytes, except that the MSB of each byte functions as
an enable bit (enable = “1”). These enable bits specify which
alarm registers (seconds, minutes, etc.) are used to make
the comparison. Note that there is no alarm byte for year.
The alarm function works as a comparison between the
alarm registers and the RTC registers. As the RTC
advances, the alarm will be triggered once a match occurs
between the alarm registers and the RTC registers. Any one
alarm register, multiple registers, or all registers can be
enabled for a match. See “Device Operation” on page 13
and “Application Section” on page 21 for more information.
Control Registers (Non-Volatile)
The Control Bits and Registers described under this section
are non-volatile.
BL Register
BP2, BP1, BP0 - Block Protect Bits
The Block Protect Bits, BP2, BP1 and BP0, determine which
blocks of the array are write protected. A write to a protected
block of memory is ignored. The block protect bits will
prevent write operations to one of eight segments of the
array. The partitions are described in Table 3.
TABLE 3.
PROTECTED ADDRESSES
ISL12025
ARRAY LOCK
000
None (Default)
None
001
010
011
100
101
110
111
180h – 1FFh
100h – 1FFh
000h – 1FFh
000h – 03Fh
000h – 07Fh
000h – 0FFh
000h – 1FFh
Upper 1/4
Upper 1/2
Full Array
First 4 Pages
First 8 Pages
First 16 Pages
Full Array
Oscillator Compensation Registers
There are two trimming options.
- ATR. Analog Trimming Register
- DTR. Digital Trimming Register
These registers are non-volatile. The combination of analog
and digital trimming can give up to -64ppm to +110ppm of
total adjustment.
ATR Register - ATR5, ATR4, ATR3, ATR2, ATR1,
ATR0: Analog Trimming Register
Six analog trimming bits, ATR0 to ATR5, are provided in
order to adjust the on-chip load capacitance value for
frequency compensation of the RTC. Each bit has a different
weight for capacitance adjustment. For example, using a
Citizen CFS-206 crystal with different ATR bit combinations
provides an estimated ppm adjustment range from -34ppm
to +80ppm to the nominal frequency compensation.
X1
CX1
X2
CX2
CRYSTAL
OSCILLATOR
FIGURE 12. DIAGRAM OF ATR
The effective on-chip series load capacitance, CLOAD,
ranges from 4.5pF to 20.25pF with a mid-scale value of
12.5pF (default). CLOAD is changed via two digitally
controlled capacitors, CX1 and CX2, connected from the X1
and X2 pins to ground (see Figure 12). The value of CX1 and
CX2 is given by the following formula:
CX = (16 b5 + 8 b4 + 4 b3 + 2 b2 + 1 b1 + 0.5 b0 + 9)pF
(EQ. 1)
The effective series load capacitance is the combination of
CX1 and CX2:
CLOAD
=
----------------1------------------
-----1-----
CX1
+
C-----1X----2-⎠⎞
(EQ. 2)
CLOAD
=
-1--6--------b---5----+-----8-------b---4-----+----4-------b----3----+----2-2-------b---2----+----1--------b---1----+-----0---.-5--------b---0----+----9--⎠⎞
p
F
For example:
CLOAD(ATR = 00000) = 12.5pF,
CLOAD(ATR = 100000) = 4.5pF, and
CLOAD(ATR = 011111) = 20.25pF.
The entire range for the series combination of load
capacitance goes from 4.5pF to 20.25pF in 0.25pF steps.
Note that these are typical values.
DTR Register - DTR2, DTR1, DTR0: Digital
Trimming Register
The digital trimming Bits DTR2, DTR1 and DTR0 adjust the
number of counts per second and average the ppm error to
achieve better accuracy.
DTR2 is a sign bit, where:
DTR2 = 0 means frequency compensation is >0.
DTR2 = 1 means frequency compensation is <0.
DTR1 and DTR0 are scale bits. DTR1 gives 10ppm
adjustment and DTR0 gives 20ppm adjustment.
12 FN6371.1
October 18, 2006

12 Page





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