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ISL22329 Schematic ( PDF Datasheet ) - Intersil Corporation

Teilenummer ISL22329
Beschreibung Dual Digitally Controlled Potentiometers
Hersteller Intersil Corporation
Logo Intersil Corporation Logo 




Gesamt 12 Seiten
ISL22329 Datasheet, Funktion
ISL22329
® Dual Digitally Controlled Potentiometers (XDCP™)
Data Sheet
September 26, 2006
FN6330.1
Low Noise, Low Power, I2C® Bus, 128 Taps,
Wiper Only
The ISL22329 integrates two digitally controlled
potentiometers (DCP) and non-volatile memory on a
monolithic CMOS integrated circuit.
The digitally controlled potentiometers are implemented with
a combination of resistor elements and CMOS switches. The
position of the wipers are controlled by the user through the
I2C bus interface. Each potentiometer has an associated
volatile Wiper Register (WR) and a non-volatile Initial Value
Register (IVR) that can be directly written to and read by the
user. The contents of the WR controls the position of the
wiper. At power-up the device recalls the contents of the two
DCP’s IVR to the corresponding WRs.
The DCPs can be used as a voltage divider in a wide variety
of applications including control, parameter adjustments, AC
measurement and signal processing.
Pinout
ISL22329
(10 LD MSOP)
TOP VIEW
www.DataSheet4U.com
A2
SCL
SDA
GND
RW1
1
2
3
4
5
10 RW0
9 SHDN
8 VCC
7 A1
6 A0
Features
• Two potentiometers in one package
• 128 resistor taps
• I2C serial interface
- Three address pins, up to eight devices/bus
• Non-volatile storage of wiper position
• Wiper resistance: 70typical @ 3.3V
• Shutdown mode
• Shutdown current 5µA max
• Power supply: 2.7V to 5.5V
• 50kor 10ktotal resistance
• High reliability
- Endurance: 1,000,000 data changes per bit per register
- Register data retention: 50 years @ T < +55°C
• 10 Ld MSOP
• Pb-free plus anneal product (RoHS compliant)
Ordering Information
PART NUMBER
PART MARKING
RESISTANCE OPTION
(k)
TEMP. RANGE
(°C)
PACKAGE
PKG. DWG. #
ISL22329UFU10Z
(Notes 1, 2)
329UZ
50
-40 to +125
10 Ld MSOP
M10.118
(Pb-free)
ISL22329WFU10Z
(Notes 1, 2)
329WZ
10
-40 to +125
10 Ld MSOP
M10.118
(Pb-free)
NOTES:
1. Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are
MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
2. Add “-TK” suffix for 1,000 Tape and Reel option
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) and XDCP are registered trademarks of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2006. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.






ISL22329 Datasheet, Funktion
ISL22329
Operating Specifications Over the recommended operating conditions unless otherwise specified. (Continued)
SYMBOL
PARAMETER
TEST CONDITIONS
TYP
MIN (NOTE 5) MAX
UNIT
tSU:A A2, A1 and A0 Setup Time
Before START condition
600
ns
tHD:A A2, A1 and A0 Hold Time
After STOP condition
600
ns
NOTES:
5. Typical values are for TA = +25°C and 3.3V supply voltage.
6. LSB: [V(RW)127 – V(RW)0]/127. V(RW)127 and V(RW)0 are V(RW) for the DCP register set to 7F hex and 00 hex respectively. LSB is the
incremental voltage when changing from one tap to an adjacent tap.
7. ZS error = V(RW)0/LSB.
8. FS error = [V(RW)127 – VCC]/LSB.
9. DNL = [V(RW)i – V(RW)i-1]/LSB-1, for i = 1 to 127. i is the DCP register setting.
10. INL = [V(RW)i – i • LSB – V(RW)0]/LSB for i = 1 to 127.
11. VMATCH = [V(RWx)i – V(RWy)i]/LSB, for i = 1 to 127, x = 0 to 1 and y = 0 to 1.
12.
TCV
=
-------M-----a----x----(--V----(---R-----W------)--i--)---–-----M-----i--n----(--V-----(--R-----W------)--i--)------ × ----1----0---6----- for i = 16 to 112 decimal, T = -40°C to +125°C. Max( ) is the maximum value of the wiper
[Max(V(RW)i) + Min(V(RW)i)] ⁄ 2 165°C voltage and Min ( ) is the minimum value of the wiper voltage over the temperature range.
13. This parameter is not 100% tested.
14. tWC is the time from a valid STOP condition at the end of a Write sequence of I2C serial interface, to the end of the self-timed internal non-
volatile write cycle.
SDA vs SCL Timing
tF
tHIGH
tLOW
tR
tsp
tHD:STO
SCL
tSU:STA
SDA
(INPUT TIMING)
SDA
(OUTPUT TIMING)
tSU:DAT
tHD:STA
tHD:DAT
tAA tDH
tSU:STO
tBUF
A0 and A1 Pin Timing
SCL
START
CLK 1
STOP
SDA
A0, A1
tSU:A
tHD:A
6 FN6330.1
September 26, 2006

6 Page









ISL22329 pdf, datenblatt
ISL22329
Mini Small Outline Plastic Packages (MSOP)
N
E1 E
INDEX
AREA
A A2
12
TOP VIEW
-B-
0.20 (0.008) A B C
GAUGE
PLANE
0.25
(0.010)
4X θ
R1
R
SEATING
PLANE -C-
L
4X θ
L1
A1 -H-
b
e
D
SEATING
0.10 (0.004) C PLANE
-A-
0.20 (0.008) C
C
SIDE VIEW
a
0.20 (0.008) C D
CL
E1 -B-
END VIEW
NOTES:
1. These package dimensions are within allowable dimensions of
JEDEC MO-187BA.
2. Dimensioning and tolerancing per ANSI Y14.5M-1994.
3. Dimension “D” does not include mold flash, protrusions or gate
burrs and are measured at Datum Plane. Mold flash, protrusion
and gate burrs shall not exceed 0.15mm (0.006 inch) per side.
4. Dimension “E1” does not include interlead flash or protrusions
and are measured at Datum Plane. - H - Interlead flash and
protrusions shall not exceed 0.15mm (0.006 inch) per side.
5. Formed leads shall be planar with respect to one another within
0.10mm (.004) at seating Plane.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “b” does not include dambar protrusion. Allowable
dambar protrusion shall be 0.08mm (0.003 inch) total in excess
of “b” dimension at maximum material condition. Minimum space
between protrusion and adjacent lead is 0.07mm (0.0027 inch).
10. Datums -A - and - B - to be determined at Datum plane
-H- .
11. Controlling dimension: MILLIMETER. Converted inch dimen-
sions are for reference only
M10.118 (JEDEC MO-187BA)
10 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE
INCHES
MILLIMETERS
SYMBOL MIN MAX MIN MAX NOTES
A
0.037 0.043 0.94
1.10
-
A1
0.002 0.006 0.05
0.15
-
A2
0.030 0.037 0.75
0.95
-
b
0.007 0.011 0.18
0.27
9
c
0.004 0.008 0.09
0.20
-
D
0.116 0.120 2.95
3.05
3
E1
0.116 0.120 2.95
3.05
4
e 0.020 BSC
0.50 BSC
-
E
0.187 0.199 4.75
5.05
-
L
0.016 0.028 0.40
0.70
6
L1 0.037 REF
0.95 REF
-
N 10
10 7
R
0.003
-
0.07
-
-
R1
0.003
-
0.07
-
θ 5o 15o 5o 15o
α 0o 6o 0o 6o
-
-
-
Rev. 0 12/02
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
12 FN6330.1
September 26, 2006

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