|
|
Teilenummer | HI1175 |
|
Beschreibung | Flash A/D Converter | |
Hersteller | Intersil Corporation | |
Logo | ||
Gesamt 13 Seiten HI1175
August 1997
8-Bit, 20 MSPS, Flash A/D Converter
Features
Description
• Resolution . . . . . . . . . . . . . . . . . . 8-Bit ±0.3 LSB (DNL)
• Maximum Sampling Frequency . . . . . . . . . . . 20 MSPS
• Low Power Consumption . . . .60mW (at 20 MSPS Typ)
(Reference Current Excluded)
• Built-In Sample and Hold Circuit
• Built-In Reference Voltage Self Bias Circuit
• Three-State TTL Compatible Output
• Single +5V Power Supply
• Low Input Capacitance . . . . . . . . . . . . . . . . . 11pF (Typ)
• Reference Impedance . . . . . . . . . . . . . . . . . . 300Ω (Typ)
• Evaluation Board Available (HI1175-EV)
• Low Cost
• Direct Replacement for the Sony CXD1175
The HI1175 is an 8-bit, analog-to-digital converter built in a
1.4µm CMOS process. The low power, low differential gain
and phase, high sampling rate, and single 5V supply make
the HI1175 ideal for video and imaging applications.
The adoption of a 2-step flash architecture achieves low
power consumption (60mW) at a maximum conversion
speed of 20 MSPS (Min), 35 MSPS typical with only a 2.5
clock cycle data latency. The HI1175 also features digital
output enable/disable and a built in voltage reference. The
HI1175 can be configured to use the internal reference or an
external reference if higher precision is required.
Ordering Information
TEMP.
PART NUMBER RANGE (oC)
PACKAGE
HI1175JCP
-40 to 85 24 Ld PDIP
PKG.
NO.
E24.4-S
Applications
• Video Digitizing
www.DataSheet4U.com
• Image Scanners
• Multimedia
• PC Video Capture
• TV Set Top Boxes
• Personal Communication
Systems (PCS)
HI1175JCB
HI1175-EV
-40 to 85
25
24 Ld SOIC
M24.2-S
Evaluation Board
Pinout
HI1175 (PDIP, SOIC)
TOP VIEW
OE 1
DVSS
D0 (LSB)
D1
2
3
4
D2 5
D3 6
D4 7
D5 8
D6 9
D7 (MSB) 10
DVDD 11
CLK 12
24 DVSS
23 VRB
22 VRBS
21 AVSS
20 AVSS
19 VIN
18 AVDD
17 VRT
16 VRTS
15 AVDD
14 AVDD
13 DVDD
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
4-1069
File Number 3577.6
Timing Diagrams
ANALOG INPUT
HI1175
VI (1)
VI (2)
VI (3)
VI (4)
EXTERNAL CLOCK
UPPER COMPARATOR BLOCK
UPPER DATA
S (1)
C (1) S (2) C (2)
S (3) C (3)
S (4) C (4)
MD (0)
MD (1)
MD (2)
MD (3)
LOWER REFERENCE VOLTAGE
LOWER COMPARATOR BLOCK A
LOWER DATA A
RV (0)
RV (1)
RV (2)
RV (3)
S (1)
H (1)
LD (-1)
C (1)
S (3)
H (3)
LD (1)
C (3)
LOWER COMPARATOR BLOCK B
LOWER DATA B
H (0)
C (0) S (2)
LD (-2)
H (2)
LD (0)
C (2)
S (4)
H (4)
LD (2)
DIGITAL OUTPUT
Typical Performance Curves
20
15
OUT (-2)
OUT (-1)
FIGURE 2.
OUT (0)
OUT (1)
20
VPP = 5.0V, VRT = 2.5V, VRB = 0.5V
TA = 25oC, VIN = 2VP-P
15
100
10
10 50
5
4.0 4.5
5.0 5.5
POWER SUPPLY VOLTAGE (V)
FIGURE 3. SUPPLY CURRENT vs SUPPLY VOLTAGE
5
05
10 15 20 25 30 35
SAMPLING RATE (MSPS)
FIGURE 4. SUPPLY CURRENT AND POWER vs SAMPLING
RATE
4-1074
6 Page HI1175
Static Performance Definitions
Offset, full scale, and gain all use a measured value of the
internal voltage reference to determine the ideal plus and
minus full scale values. The results are all displayed in LSBs.
Offset Error (EOB)
The first code transition should occur at a level 1/2 LSB
above the bottom reference voltage. Offset is defined as the
deviation of the actual code transition from this point. Note
that this is adjustable to zero.
Full Scale Error (EOT)
The last code transition should occur for a analog input that
is 11/2 LSBs below full scale. Full scale error is defined as
the deviation of the actual code transition from this point.
Differential Linearity Error (DNL)
DNL is the worst case deviation of a code width from the
ideal value of 1 LSB. The converter is guaranteed to have no
missing codes.
Integral Linearity Error (INL)
INL is the worst case deviation of a code center from a best
fit straight line calculated from the measured data.
Dynamic Performance Definitions
Fast Fourier Transform (FFT) techniques are used to
evaluate the dynamic performance of the HI1175. A low dis-
tortion sine wave is applied to the input, it is sampled, and
the output is stored in RAM. The data is then transformed
into the frequency domain with a 1024 point FFT and ana-
lyzed to evaluate the dynamic performance of the A/D. The
sine wave input to the part is -0.5dB down from fullscale for
all these tests. The distortion numbers are quoted in dBc
(decibels with respect to carrier) and DO NOT include any
correction factors for normalizing to fullscale.
Signal-to-Noise Ratio (SNR)
SNR is the measured RMS signal to RMS noise at a speci-
fied input and sampling frequency. The noise is the RMS
sum of all of the spectral components except the fundamen-
tal and the first five harmonics.
Signal-to-Noise + Distortion Ratio (SINAD)
SINAD is the measured RMS signal to RMS sum of all other
spectral components below the Nyquist frequency excluding
DC.
Effective Number Of Bits (ENOB)
The effective number of bits (ENOB) is derived from the
SINAD data. ENOB is calculated from:
Total Harmonic Distortion
This is the ratio of the RMS sum of the first 5 harmonic com-
ponents to the RMS value of the measured input signal.
2nd and 3rd Harmonic Distortion
This is the ratio of the RMS value of the 2nd and 3rd
harmonic component respectively to the RMS value of the
measured input signal.
Spurious Free Dynamic Range (SFDR)
SFDR is the ratio of the fundamental RMS amplitude to the
RMS amplitude of the next largest spur or spectral compo-
nent. If the harmonics are buried in the noise floor it is the
largest peak.
Full Power Input Bandwidth
Full power bandwidth is the frequency at which the ampli-
tude of the digitally reconstructed output has decreased 3dB
below the amplitude of the input sine wave. The input sine
wave has a peak-to-peak amplitude equal to the reference
voltage. The bandwidth given is measured at the specified
sampling frequency.
Timing Definitions
Sampling Delay (tSD)
Sampling delay is the time delay between the external
sample command (the falling edge of the clock) and the time
at which the signal is actually sampled. This delay is due to
internal clock path propagation delays.
Aperture Jitter (tAJ)
This is the RMS variation in the sampling delay due to
variation of internal clock path delays.
Data Latency (tLAT)
After the analog sample is taken, the data on the bus is
available after 2.5 cycles of the clock. This is due to the
architecture of the converter where the data has to ripple
through the stages. This delay is specified as the data
latency. After the data latency time, the data representing
each succeeding sample is output at the following clock
pulse. The digital data lags the analog input by 2.5 cycles.
Output Data Delay (tD)
Output Data Delay is the delay time from when the data is
valid (rising clock edge) to when it shows up at the output
bus. This is due to internal delays at the digital output.
ENOB = (SINAD - 1.76 + VCORR) / 6.02,
where: VCORR = 0.5dB.
4-1080
12 Page | ||
Seiten | Gesamt 13 Seiten | |
PDF Download | [ HI1175 Schematic.PDF ] |
Teilenummer | Beschreibung | Hersteller |
HI117 | PNP EPITAXIAL PLANAR TRANSISTOR | Hi-Sincerity Mocroelectronics |
HI1171 | High Speed D/A Converter | Intersil Corporation |
HI1172 | Video A/D Converter | Intersil Corporation |
HI1175 | Flash A/D Converter | Intersil Corporation |
HI1176 | Flash A/D Converter | Harris |
Teilenummer | Beschreibung | Hersteller |
CD40175BC | Hex D-Type Flip-Flop / Quad D-Type Flip-Flop. |
Fairchild Semiconductor |
KTD1146 | EPITAXIAL PLANAR NPN TRANSISTOR. |
KEC |
www.Datenblatt-PDF.com | 2020 | Kontakt | Suche |