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HI1171 Schematic ( PDF Datasheet ) - Intersil Corporation

Teilenummer HI1171
Beschreibung High Speed D/A Converter
Hersteller Intersil Corporation
Logo Intersil Corporation Logo 




Gesamt 7 Seiten
HI1171 Datasheet, Funktion
HI1171
August 1997
8-Bit, 40 MSPS, High Speed D/A Converter
Features
Description
• Throughput Rate . . . . . . . . . . . . . . . . . . . . . . . . . 40MHz
• Resolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-Bit
• Integral Linearity Error . . . . . . . . . . . . . . . . . . 0.25 LSB
• Low Glitch Noise
• Single Supply Operation . . . . . . . . . . . . . . . . . . . . . . +5V
• Low Power Consumption (Max) . . . . . . . . . . . . . .80mW
• Evaluation Board Available (HI1171-EV)
• Direct Replacement for the Sony CXD1171
Applications
• Wireless Telecommunications
The HI1171 is an 8-bit, 40MHz, high speed D/A converter.
The converter incorporates an 8-bit input data register with
blanking capability, and current outputs. The HI1171 fea-
tures low glitch outputs. The architecture is a current cell
arrangement to provide low linearity errors.
The HI1171 is available in an Industrial temperature range
and is offered in a 24 lead (200 mil) SOIC plastic package.
For dual version, please refer to the HI1177 Data Sheet.
For triple version, please refer to the HI1178 Data Sheet.
Ordering Information
PART
NUMBER
TEMP. RANGE
(oC)
PACKAGE
PKG. NO.
• Signal Reconstruction
HI1171JCB
-40 to 85 24 Ld SOIC M24.2-S
• Direct Digital Synthesis
• Imaging
HI1171-EV
25 Evaluation Board
• Presentation and Broadcast Video
• Graphics Displays
www.DataSheet4U.com
• Signal Generators
Pinout
HI1171
(SOIC)
TOP VIEW
(LSB) D0 1
D1 2
D2 3
D3 4
D4 5
D5 6
D6 7
D7 8
BLNK 9
DVSS 10
VB 11
CLK 12
24 DVDD
23 DVDD
22 AVDD
21 IOUT2
20 IOUT1
19 AVDD
18 AVDD
17 VG
16 VREF
15 IREF
14 AVSS
13 DVSS
Typical Application Circuit
+5V
HI1171
+5V
0.1µF
DVDD (23, 24)
(18, 19, 22) AVDD
0.1µF
D7
D7 (MSB)(8)
(17) VG
0.1µF
D6 D6 (7)
D5 D5 (6)
(16) VREF
1k
D4 D4 (5)
D3 D3 (4)
D2 D2 (3)
D1 D1 (2)
(20) IOUT1
D0 D0 (LSB) (1)
D/A
OUT
200
0.1µF
CLK (12)
VB (11)
BLNK (9)
DVSS (10, 13)
(15) IREF
(21) IOUT2
(14) AVSS
3.3k
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
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File Number 3662.2






HI1171 Datasheet, Funktion
HI1171
Pin Descriptions (Continued)
24 PIN
SOIC
PIN
NAME
PIN DESCRIPTION
17
18, 19, 22
20
21
23, 24
VG
AVDD
IOUT1
IOUT2
DVDD
Voltage Ground, connect a 0.1µF capacitor to AVDD.
Analog Supply 4.75V to 7V.
Current Output Pin.
Current Output pin used for a virtual ground connection. Usually connected to AVSS.
Digital Supply 4.75V to 7V.
Detailed Description
The HI1171 is an 8-bit, current out D/A converter. The DAC
can convert at 40MHz and run on a single +5V supply. The
architecture is an encoded, switched current cell
arrangement.
Voltage Output Mode
The output current of the HI1171 can be converted into a volt-
age by connecting an external resistor to IOUT1. To calculate
the output resistor use the following equation:
As the values of both ROUT and RREF increase, power
consumption is decreased, but glitch energy and output
settling time is increased.
Clock Phase Relationship
The internal latch is closed when the clock line is high. The
latch can be cleared by the BLNK line. When BLNK is set
(HIGH) the contents of the internal data latch will be cleared.
When BLNK is low data is updated by the CLK.
ROUT = VFS /IFS,
where VFS can range from +0.5V to +2.0V and IFS can
range from 0mA to 15mA.
In setting the output current the IREF pin should have a resistor
connected to it that is 16 times greater than the output resistor:
RREF = 16 x ROUT
Noise Reduction
To reduce power supply noise separate analog and digital
power supplies should be used with 0.1µF ceramic capaci-
tors placed as close to the body of the HI1171 as possible.
The analog (AVSS) and digital (DVSS) ground returns should
be connected together back at the power supply to ensure
proper operation from power up.
Test Circuits
8-BIT
COUNTER
WITH LATCH
CLK
40MHz
SQUARE WAVE
(LSB) D0
1
2
D7
8
BLK
9
0.1µF
11
VB
12
CLK
IO
20
VG
17
0.1µF
VREF
16
2V
IREF
15
AVDD
OSCILLOSCOPE
200
1k
AVSS
3.3k
FIGURE 5. MAXIMUM CONVERSION SPEED TEST CIRCUIT
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
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