PDF AM50DL128CH Data sheet ( Hoja de datos )

Número de pieza	AM50DL128CH
Descripción	STACKED MULTI-CHIP PACKAGE (MCP) FLASH MEMORY AND SRAM
Fabricantes	AMD
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Am50DL128CH Data Sheet -XO\ 7KH IROORZLQJ GRFXPHQW VSHFLILHV 6SDQVLRQ PHPRU\ SURGXFWV WKDW DUH QRZ RIIHUHG E\ ERWK $GYDQFHG 0LFUR 'HYLFHV DQG )XMLWVX $OWKRXJK WKH GRFXPHQW LV PDUNHG ZLWK WKH QDPH RI WKH FRPSDQ\ WKDW RULJ LQDOO\ GHYHORSHG WKH VSHFLILFDWLRQ WKHVH SURGXFWV ZLOO EH RIIHUHG WR FXVWRPHUV RI ERWK $0' DQG )XMLWVX Continuity of Specifications 7KHUH LV QR FKDQJH WR WKLV GDWDVKHHW DV D UHVXOW RI RIIHULQJ WKH GHYLFH DV D 6SDQVLRQ SURGXFW $Q\ FKDQJHV WKDW KDYH EHHQ PDGH DUH WKH UHVXOW RI QRUPDO GDWDVKHHW LPSURYHPHQW DQG DUH QRWHG LQ WKH GRFXPHQW UHYLVLRQ VXPPDU\ ZKHUH VXSSRUWHG )XWXUH URXWLQH UHYLVLRQV ZLOO RFFXU ZKHQ DSSURSULDWH DQG FKDQJHV ZLOO EH QRWHG LQ D UHYLVLRQ VXPPDU\ Continuity of Ordering Part Numbers $0' DQG )XMLWVX FRQWLQXH WR VXSSRUW H[LVWLQJ SDUW QXPEHUV EHJLQQLQJ ZLWK ³$P´ DQG ³0%0´ 7R RUGHU WKHVH SURGXFWV SOHDVH XVH RQO\ WKH 2UGHULQJ 3DUW 1XPEHUV OLVWHG LQ WKLV GRFXPHQW For More Information www.DataSheet4U.com 3OHDVH FRQWDFW \RXU ORFDO $0' RU )XMLWVX VDOHV RIILFH IRU DGGLWLRQDO LQIRUPDWLRQ DERXW 6SDQVLRQ PHPRU\ VROXWLRQV Publication Number 30776 Revision A Amendment 0 Issue Date October 6, 2003 1 page ADVANCE INFORMATION TABLE OF CONTENTS Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 5 MCP Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . 5 Flash Memory Block Diagram . . . . . . . . . . . . . . . . 6 Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . . 7 Special Package Handling Instructions .................................... 7 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 9 MCP Device Bus Operations . . . . . . . . . . . . . . . . 10 Table 1. Device Bus Operations—Flash Word Mode .....................11 Flash Device Bus Operations . . . . . . . . . . . . . . . 12 Word Configuration ................................................................. 12 Requirements for Reading Array Data ................................... 12 Writing Commands/Command Sequences ............................ 12 Accelerated Program Operation .......................................... 12 Autoselect Functions ........................................................... 12 Simultaneous Read/Write Operations with Zero Latency ....... 12 Standby Mode ........................................................................ 12 Automatic Sleep Mode ........................................................... 13 RESET#: Hardware Reset Pin ............................................... 13 Output Disable Mode .............................................................. 13 Table 2. Am29DL640H Sector Architecture ....................................14 Table 3. Bank Address ....................................................................17 Table 4. SecSi™ Sector Addresses ...............................................17 Sector/Sector Block Protection and Unprotection .................. 18 Table 5. Am29DL640H Boot Sector/Sector Block Addresses for Pro- tection/Unprotection ........................................................................18 Write Protect (WP#) ................................................................ 18 Table 6. WP#/ACC Modes ..............................................................19 Temporary Sector Unprotect .................................................. 19 Figure 1. Temporary Sector Unprotect Operation ...........................19 Figure 2. In-System Sector Protect/Unprotect Algorithms ..............20 SecSi™ (Secured Silicon) Sector Flash Memory Region ............................................................ 21 Figure 3. SecSi Sector Protect Verify ..............................................22 Hardware Data Protection ...................................................... 22 Low VCC Write Inhibit ........................................................... 22 Write Pulse “Glitch” Protection ............................................ 22 Logical Inhibit ...................................................................... 22 Power-Up Write Inhibit ......................................................... 22 Common Flash Memory Interface (CFI) . . . . . . . 22 Table 7. CFI Query Identification String ..........................................23 Table 8. System Interface String .....................................................23 Table 9. Device Geometry Definition ..............................................24 Table 10. Primary Vendor-Specific Extended Query ......................25 Flash Command Definitions . . . . . . . . . . . . . . . . 26 Reading Array Data ................................................................ 26 Reset Command ..................................................................... 26 Autoselect Command Sequence ............................................ 26 Enter SecSi™ Sector/Exit SecSi Sector Command Sequence .............................................................. 26 Word Program Command Sequence ..................................... 27 Unlock Bypass Command Sequence .................................. 27 Figure 4. Program Operation ..........................................................28 Chip Erase Command Sequence ........................................... 28 Sector Erase Command Sequence ........................................ 28 Figure 5. Erase Operation ...............................................................29 Erase Suspend/Erase Resume Commands ........................... 29 Table 11. Am29DL640H Command Definitions ..............................30 Flash Write Operation Status . . . . . . . . . . . . . . . 31 DQ7: Data# Polling ................................................................. 31 Figure 6. Data# Polling Algorithm .................................................. 31 RY/BY#: Ready/Busy# ............................................................ 32 DQ6: Toggle Bit I .................................................................... 32 Figure 7. Toggle Bit Algorithm ........................................................ 32 DQ2: Toggle Bit II ................................................................... 33 Reading Toggle Bits DQ6/DQ2 ............................................... 33 DQ5: Exceeded Timing Limits ................................................ 33 DQ3: Sector Erase Timer ....................................................... 33 Table 12. Write Operation Status ................................................... 34 Absolute Maximum Ratings . . . . . . . . . . . . . . . . 35 Figure 8. Maximum Negative Overshoot Waveform ...................... 35 Figure 9. Maximum Positive Overshoot Waveform ........................ 35 ESD Immunity ......................................................................... 36 Flash DC Characteristics . . . . . . . . . . . . . . . . . . 37 CMOS Compatible .................................................................. 37 pSRAM DC & Operating Characteristics . . . . . . 38 Flash DC Characteristics . . . . . . . . . . . . . . . . . . 39 Figure 10. ICC1 Current vs. Time (Showing Active and Automatic Sleep Currents) ............................................................. 39 Figure 11. Typical ICC1 vs. Frequency ............................................ 39 Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Figure 12. Test Setup .................................................................... 40 Figure 13. Input Waveforms and Measurement Levels ................. 40 pSRAM AC Characteristics . . . . . . . . . . . . . . . . . 41 CE#s Timing ........................................................................... 41 Figure 14. Timing Diagram for Alternating Between Pseudo SRAM to Flash ................................................... 41 Read-Only Operations ........................................................... 42 Figure 15. Read Operation Timings ............................................... 42 Hardware Reset (RESET#) .................................................... 43 Figure 16. Reset Timings ............................................................... 43 Erase and Program Operations .............................................. 44 Figure 17. Program Operation Timings .......................................... 45 Figure 18. Accelerated Program Timing Diagram .......................... 45 Figure 19. Chip/Sector Erase Operation Timings .......................... 46 Figure 20. Back-to-back Read/Write Cycle Timings ...................... 47 Figure 21. Data# Polling Timings (During Embedded Algorithms) . 47 Figure 22. Toggle Bit Timings (During Embedded Algorithms) ...... 48 Figure 23. DQ2 vs. DQ6 ................................................................. 48 Temporary Sector Unprotect .................................................. 49 Figure 24. Temporary Sector Unprotect Timing Diagram .............. 49 Figure 25. Sector/Sector Block Protect and Unprotect Timing Diagram ............................................................. 50 Alternate CE#f Controlled Erase and Program Operations .... 51 Figure 26. Flash Alternate CE#f Controlled Write (Erase/Program) Operation Timings .......................................................................... 52 Read Cycle ............................................................................. 53 Figure 27. Pseudo SRAM Read Cycle ........................................... 53 Figure 28. Page Read Timing ........................................................ 54 Write Cycle ............................................................................. 55 Figure 29. Pseudo SRAM Write Cycle—WE# Control ................... 55 Figure 30. Pseudo SRAM Write Cycle—CE#1ps Control .............. 56 Figure 31. Pseudo SRAM Write Cycle— UB#s and LB#s Control .................................................................. 57 Flash Erase And Programming Performance . . 58 October 6, 2003 Am50DL128CH 3 5 Page ADVANCE INFORMATION ORDERING INFORMATION The order number (Valid Combination) is formed by the following: Am50DL128 C H 70 I T TAPE AND REEL T = 7 inches S = 13 inches TEMPERATURE RANGE I = Industrial (–40°C to +85°C) SPEED OPTION See “Product Selector Guide” on page 5 FLASH PROCESS TECHNOLOGY H = 0.13 µm PSEUDO SRAM DEVICE DENSITY C = 64 Mbits AMD DEVICE NUMBER/DESCRIPTION Am50DL128CH Stacked Multi-Chip Package (MCP) Flash Memory and SRAM Two Am29DL640H 64 Megabit (4 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memories and 64 Mbit (4 M x 16-Bit) Pseudo Static RAM with Page Mode 88-Ball Fine Pitch Ball Grid Array, 11.6 x 8, 0.80 mm pitch package (FTA088) Valid Combinations Valid Combinations list configurations planned to be supported in vol- ume for this device. Consult the local AMD or Fujitsu sales office to confirm availability of specific valid combinations and to check on newly released combinations. Valid Combinations Order Number Package Marking Am50DL128CH56I M50000004M Am50DL128CH70I T,S M50000004N Am50DL128CH85I M50000004P October 6, 2003 Am50DL128CH 9 11 Page

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