PDF FIN224AC Data sheet ( Hoja de datos )

Número de pieza	FIN224AC
Descripción	USerDes 22-Bit Bi-Directional Serializer/Deserializer
Fabricantes	Fairchild Semiconductor
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September 2006 FIN224AC µSerDes™ 22-Bit Bi-Directional Serializer/Deserializer Features FIN224AC to FIN24AC Comparison ■ Industry smallest 22-bit Serializer/ Deserializer pair ■ Up to 20% power reduction ■ Low power for minimum impact on battery life – Multiple power-down modes ■ 100nA in standby mode, 5mA typical operating conditions ■ Highly rolled LVCMOS edge rate option to meet regulatory requirements ■ Cable reduction: 25:4 or greater ■ Double wide CKP pulse on FIN224AC, Mode 3 ■ Rolled edge rate for deserializer outputs on FIN224AC, for single display applications ■ Same voltage range ■ Same pinout and package General Description ■ Differential signaling: – –90dBm EMI when using CTL in lab conditions – Minimized shielding – Minimized EMI filter – Minimum susceptibility to external interference ■ Up to 22 bits in either direction The FIN224AC µSerDes™ is a low-power Serializer/ Deserializer (SerDes) that can help minimize the cost and power of transferring wide signal paths. Through the use of serialization, the number of signals transferred from one point to another can be significantly reduced. Typical reduction is 4:1 to 6:1 for unidirectional paths. ■ Up to 26MHz parallel interface operation For bidirectional operation, using half duplex for multiple ■ Voltage translation from 1.65V to 3.6V sources, it is possible to reach signal reduction close to ■ High ESD protection: > 15kV HBM 10:1. Through the use of differential signaling, shielding and EMI filters can also be minimized, further reducing ■ Parallel I/O power supply (VDDP) range, 1.65V - 3.w6wVw.DataSheett4hU.ecomcost of serialization. The differential signaling is also ■ Can support Microcontroller or RGB pixel interface important for providing a noise-insensitive signal that can Applications withstand radio and electrical noise sources. Major reduction in power consumption allows minimal impact ■ Image sensors ■ Small displays – LCD, cell phone, digital camera, portable gaming, printer, PDA, video camera, automotive on battery life in ultra-portable applications. A unique word boundary technique assures that the actual word boundary is identified when the data is deserialized. This guarantees that each word is correctly aligned at the deserializer on a word-by-word basis through a unique sequence of clock and data that is not repeated except at the word boundary. It is possible to use a single PLL for most applications including bi-directional operation. Ordering Information Order Number FIN224ACGFX Package Number BGA042 FIN224ACMLX MLP040 Pb-Free Yes Yes Package Description 42-Ball Ultra Small Scale Ball Grid Array (USS-BGA), JEDEC MO-195, 3.5mm Wide (Slow LVCMOS Edge Rate) 40-Terminal Molded Leadless Package (MLP), Quad, JEDEC MO-220, 6mm Square (Slow LVCMOS Edge Rate) Pb-Free package per JEDEC J-STD-020B. BGA and MLP packages available in tape and reel only. µSerDesTM is a trademark of Fairchild Semiconductor Corporation. ©2006 Fairchild Semiconductor Corporation FIN224AC Rev. 1.0.7 1 www.fairchildsemi.com 1 page Control Logic Circuitry The FIN224AC has the ability to be used as a 22-bit seri- alizer or a 22-bit deserializer. Pins S1 and S2 must be set to accommodate the clock reference input frequency range of the serializer. Table 1 shows the pin program- ming of these options based on the S1 and S2 control pins. The DIRI pin controls whether the device is a serial- izer or a deserializer. When DIRI is asserted LOW, the device is configured as a deserializer. When the DIRI pin is asserted HIGH, the device is configured as a serial- izer. Changing the state on the DIRI signal reverses the direction of the I/O signals and generate the opposite state signal on DIRO. For unidirectional operation the DIRI pin should be hardwired to the HIGH or LOW state and the DIRO pin should be left floating. For bi-direc- tional operation, the DIRI of the master device is driven by the system and the DIRO signal of the master is used to drive the DIRI of the slave device. Serializer/Deserializer with Dedicated I/O Variation The serialization and deserialization circuitry is set up for 24 bits. Because of the dedicated inputs and outputs, only 22 bits of data are ever serialized or deserialized. Regardless of the mode of operation, the serializer is always sending 24 bits of data plus 2 boundary bits and the deserializer is always receiving 24 bits of data and 2 word boundary bits. Bits 23 and 24 of the serializer always contain the value of zero and are discarded by the deserializer. DP[21:22] input to the serializer is dese- rialized to DP[23:24] respectively. Turn-Around Functionality The device passes and inverts the DIRI signal through the device asynchronously to the DIRO signal. Care must be taken by the system designer to ensure that no contention occurs between the deserializer outputs and the other devices on this port. Optimally the peripheral device driving the serializer should be put into a HIGH- impedance state prior to the DIRI signal being asserted. When a device with dedicated data outputs turns from a deserializer to a serializer, the dedicated outputs remain at the last logical value asserted. This value only changes if the device is once again turned around into a deserializer and the values are overwritten. Power-Down Mode: (Mode 0) Mode 0 is used for powering down and resetting the device. When both of the mode signals are driven to a LOW state, the PLL and references are disabled, differ- ential input buffers are shut off, differential output buffers are placed into a HIGH-impedance state, LVCMOS out- puts are placed into a HIGH-impedance state, and LVC- MOS inputs are driven to a valid level internally. Additionally all internal circuitry is reset. The loss of CKREF state is also enabled to ensure that the PLL only powers-up if there is a valid CKREF signal. In a typical application mode, signals of the device do not change states other than between the desired frequency range and the power-down mode. This allows for sys- tem-level power-down functionality to be implemented via a single wire for a SerDes pair. The S1 and S2 selec- tion signals that have their operating mode driven to a “logic 0” should be hardwired to GND. The S1 and S2 signals that have their operating mode driven to a “logic 1” should be connected to a system-level power-down or reset signal. Table 1. Control Logic Circuitry Mode Number S2 S1 DIRI 0 00 x 1 01 1 01 0 2 10 1 10 0 3 11 1 11 0 Description Power-Down Mode 22-Bit Serializer 2MHz to 5MHz CKREF 22-Bit Deserializer 22-Bit Serializer 5MHz to 15MHz CKREF 22-Bit Deserializer 22-Bit Serializer 10MHz to 26MHz CKREF (Divide by 2 Serial Data) (Note: FIN224C required for RGB applications) 22-Bit Serializer ©2006 Fairchild Semiconductor Corporation FIN224AC Rev. 1.0.7 5 www.fairchildsemi.com 5 Page REFCLK LCD_/WRITE_ENABLE_M GPIO_MODE TP2 TP1 LCD_/CS_M LCD_ADDRESS_M LCD17_M LCD16_M LCD15_M LCD14_M LCD13_M LCD LCD12_M LCD11_M Controller LCD10_M Out LCD9_M LCD8_M LCD7_M LCD6_M LCD5_M LCD4_M LCD3_M LCD2_M LCD1_M LCD0_M µSerDes Serializer VDDP U21 FIN224AC A6 B5 CKREF STROBE F6 F5 J6 DIRI S2 S1 J5 J4 J3 F3 J2 J1 F2 F1 E2 E1 D2 D1 C2 B1 B2 A1 C3 A2 B3 A3 C4 A4 B4 A5 DP24 DP23 DP22 DP21 DP20 DP19 DP18 DP17 DP16 DP15 DP14 DP13 DP12 DP11 DP10 DP9 DP8 DP7 DP6 DP5 DP4 DP3 DP2 DP1 DIRO B6 CKP C1 DSO+/DSI- DSO-/DSI+ CKSO- CKSO+ CKSI- CKSI+ VDDA VDDS VDDP D6 D5 C6 C5 E6 E5 2.8V F4 1.8V E4 D3 C5 C2 1nF .01uµF µSerDes DeSerializer U23 FIN224AC J6 F5 F6 S1 S2 DIRI B5 A6 STROBE CKREF B6 DIRO 2.8V 2.8V C9 .01uµF C8 C7 2.2uµF 1nF D5 D6 DSO-/DSI+ DSO+/DSI- E6 E5 CKSI- CKSI+ C6 C5 CKSO- CKSO+ F4 E4 D3 VDDA VDDS VDDP CKP DP24 DP23 DP22 DP21 DP20 DP19 DP18 DP17 DP16 DP15 DP14 DP13 DP12 DP11 DP10 DP9 DP8 DP7 DP6 DP5 DP4 DP3 DP2 DP1 C1 J5 J4 J3 F3 J2 J1 F2 F1 E2 E1 D2 D1 C2 B1 B2 A1 C3 A2 B3 A3 C4 A4 B4 A5 TP3 LCD_/WRITE_ENABLE_S LCD_/CS_S LCD_ADDRESS_S LCD17_S LCD16_S LCD15_S LCD14_S LCD13_S LCD12_S LCD11_S LCD10_S LCD9_S LCD LCD8_S Display LCD7_S LCD6_S In LCD5_S LCD4_S LCD3_S LCD2_S LCD1_S LCD0_S Assumptions: 1) 18-bit Unidirectional µController Application 2) Mode 3 Operation (10 Mhz to 20Mhz CKREF) 3) VDDP= (1.65V to 3.6V) 4) REFCLK is a continously running clock with a frequency greater than /WRITE_ENABLE. Figure 13. FIN224AC Microcontroller Base Unit LCD Unit Camera Unit GPIO FIN224AC CKREF CKSO STROBE DS DP[21:22] CKSI DP[1:20] VSYNC/HSYNC DP[23:24] DIRO DIRI S1 S2 FIN224AC CKSI CKP DS DP[23:24] CKSO DP[1:20] DP[21:22] STROBE CKREF VSYNC/HSYNC DIRO DIRI S1 S2 PwrDwn Camera/LCD Select Figure 14. Multiple Units, Unidirectional Signals in Each Direction LCD Camera Disable ©2006 Fairchild Semiconductor Corporation FIN224AC Rev. 1.0.7 11 www.fairchildsemi.com 11 Page

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