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PDF SY89831U Data sheet ( Hoja de datos )
| Número de pieza | SY89831U | |
| Descripción | Ultra-Precision 1:4 LVPECL Fanout Buffer/Translator | |
| Fabricantes | Micrel Semiconductor | |
| Logotipo |  |
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SY89831U
Ultra-Precision 1:4 LVPECL Fanout
Buffer/Translator with Internal Termination
Precision Edge®
General Description
The SY89831U is a high-speed, 2GHz differential LVPECL
1:4 fanout buffer optimized for ultra-low skew applications.
Within-device skew is guaranteed to be less than 20ps
(5ps typ.) over supply voltage and temperature. The
differential input buffer has a unique internal termination
design that allows access to the termination network
through a VT pin. This feature allows the device to easily
interface to different logic standards. A VREF-AC
reference output is included for AC-coupled applications.
The SY89831U is a part of Micrel's high-speed clock
synchronization family. For applications that require a
different I/O combination, consult Micrel’s website at:
www.micrel.com, and choose from a comprehensive
product line of high-speed, low-skew fanout buffers,
translators, and clock generators.
Datasheets and support documentation are available on
Micrel’s web site at: www.micrel.com.
Precision Edge®
Features
• Guaranteed AC performance over temperature and
voltage
− DC-to 2.5GHz throughput (typical)
− 350ps propagation delay (IN-to-Q) (typical)
− 5ps within-device skew (typical)
− 150ps rise/fall time (typical)
• Ultra-low jitter design
− 62fs RMS phase jitter (typical)
• Unique patent-pending input termination and VT pin
accepts DC- and AC-coupled differential inputs
• 800mV, 100K LVPECL typical output swing
• Power supply 2.5V ±5% or 3.3V ±10%
• Industrial temperature range: –40°C to +85°C
• Available in 16-pin (3mm x 3mm) MLF® package
Applications
• Processor clock distribution
• SONET clock distribution
• Fibre Channel clock distribution
• Gigabit Ethernet clock distribution
Precision Edge is a registered trademark of Micrel, Inc.
MicroLeadFrame and MLF are registered trademarks of Amkor Technology, Inc.
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com
January 17, 2014
Revision 7.0
[email protected] or (408) 955-1690
1 page  
Micrel, Inc.
LVPECL Output DC Electrical Characteristics(8)
VCC = 2.5V ±5% or 3.3V ±10%; RL = 50Ω to VCC − 2V; TA = –40°C to + 85°C, unless otherwise noted.
Symbol Parameter
Condition
Min.
Typ.
VOH
VOL
VOUT
VDIFF_OUT
Output HIGH Voltage (Q, /Q)
Output LOW Voltage (Q, /Q)
Output Voltage Swing (Q, /Q)
Differential Output Voltage
Swing (Q, /Q)
See Figure 1.
See Figure 2.
VCC – 1.145
VCC – 1.945
550
1100
800
1600
SY89831U
Max.
VCC – 0.895
VCC – 1.695
Units
V
V
mV
mV
LVTTL/LVCMOS DC Electrical Characteristics(8)
VCC = 2.5V ±5% or 3.3V ±10%; TA = –40°C to + 85°C, unless otherwise noted.
Symbol Parameter
Condition
VIH Input HIGH Voltage
VIL Input LOW Voltage
IIH Input HIGH Current
IIL Input LOW Current
Min.
2.0
0
–125
–300
Typ.
Max.
VCC
0.8
30
Units
V
V
µA
µA
AC Electrical Characteristics(9)
VCC = 2.5V ±5% or 3.3V ±10%; RL = 50Ω to VCC − 2V; TA = –40°C to + 85°C, unless otherwise noted.
Symbol Parameter
Condition
Min. Typ. Max. Units
fMAX
tpd
tSKEW
Maximum Frequency
Propagation
Delay
IN-to-Q
IN-to-Q
Within-Device Skew
Part-to-Part Skew
VOUT ≥ 450mV
VIN ≥ 100mV
VIN ≥ 800mV
Note 10
Note 11
2.0 2.5
GHz
390 ps
250 350
450
ps
5 20 ps
150 ps
tS
tH
tJITTER
Set-Up Time EN to IN, /IN
Hold Time
EN to IN, /IN
RMS Phase Jitter
Note 12
Note 12
Output = 622MHz
Integration Range 12kHz–20MHz
300
300
62
ps
ps
fs
tr, tf Output Rise/Fall Times
(20% to 80%)
At full output swing
70 150 225
ps
Duty Cycle
Freq. < 630MHz
48 50
52
%
Notes:
9. High-frequency AC parameters are guaranteed by design and characterization.
10. Within-device skew is measured between two different outputs under identical input transitions.
11. Part-to-part skew is defined for two parts with identical power supply voltages at the same temperature and no skew at the edges at the respective
inputs.
12. Set-up and hold times apply to synchronous applications that will enable/disable before the next clock cycle. For asynchronous applications, set-up
and hold times do not apply.
January 17, 2014
5 Revision 7.0
[email protected] or (408) 955-1690
5 Page 
Micrel, Inc.
Input Interface Applications
SY89831U
Figure 5. DC-Coupled LVPECL
Input Interface
Figure 6. AC-Coupled LVPECL
Input Interface
Figure 7. DC-Coupled CML
Input Interface
Figure 8. AC-Coupled CML
Input Interface
Figure 9. DC-Coupled LVDS
Input Interface
Figure 10. AC-Coupled LVDS
Input Interface
January 17, 2014
11 Revision 7.0
[email protected] or (408) 955-1690
11 Page | ||
| Páginas | Total 14 Páginas | |
| PDF Descargar | [ Datasheet SY89831U.PDF ] | |
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