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PDF SY58611U Data sheet ( Hoja de datos )
| Número de pieza | SY58611U | |
| Descripción | LVDS 2:1 MUX | |
| Fabricantes | Micrel Semiconductor | |
| Logotipo |  |
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SY58611U
3.2Gbps Precision, LVDS 2:1 MUX with
Internal Termination and Fail Safe Input
General Description
The SY58611U is a 2.5V, high-speed, fully differential
LVDS 2:1 MUX capable of processing clocks up to
2.5GHz and data up to 3.2Gbps. SY58611U is
optimized to provide a buffered output of the selected
Features
Precision Edge®
• Selects between two sources and provides buffered
input with less than 20ps of skew and less than 10pspp
copy of the selected input signal
total jitter. Patented MUX Isolation design reduces • Fail Safe Input
crosstalk and provides superior signal integrity.
– Prevents output from oscillating when input is
The differential inputs include Micrel’s unique, 3-pin
invalid or removed
input termination architecture that interfaces to LVPECL,
LVDS or CML differential signals, (AC- or DC-coupled)
as small as 100mVPK (200mVpp) without any level-
shifting or termination resistor networks in the signal
path. For AC-coupled input interface applications, an
integrated reference voltage (VREF-AC) is provided to bias
the VT pin. The output is LVDS compatible, with rise/fall
• Guaranteed AC performance over temperature and
voltage:
– DC-to > 3.2Gbps throughput
– <420ps typical propagation delay (IN-to-Q)
– <120ps rise/fall times
• Unique, patented internal termination and VT pin
times guaranteed to be less than 120ps.
accepts DC- and AC-coupled inputs (CML, PECL,
The SY58611U operates from a 2.5V ±5% supply and is
LVDS)
guaranteed over the full industrial temperature range • Unique, patented MUX input isolation design
(–40°C to +85°C). For applications that require CMLwwwo.DrataSheet4U.cmominimizes adjacent channel crosstalk
LVPECL output, consider the SY58609U and
SY58610U, 2:1 MUX with 400mV and 800mV output
swings respectively. The SY58611U is part of Micrel’s
high-speed, Precision Edge® product line.
Datasheets and support documentation can be found on
Micrel’s web site at: www.micrel.com.
• Ultra-low jitter design
– <1psRMS cycle-to-cycle jitter
– <10psPP total jitter
– <1psRMS random jitter
– <10psPP deterministic jitter
• 2.5V ±5% power supply operation
Functional Block Diagram
• Industrial temperature range: –40°C to +85°C
• Available in 16-pin (3mm x 3mm) MLF® package
Applications
• All SONET clock distribution
• Fibre Channel clock and data distribution
• Gigabit Ethernet clock or data distribution
• Backplane distribution
Markets
• DataCom and Telecom
• Storage
• ATE
• Test and Measurement
Precision Edge is a registered trademark of Micrel, Inc.
MLF and MicroLeadFrame are registered trademarks of Amkor Technology.
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com
March 2007
M9999-030607-A
[email protected] or (408) 955-1690
1 page  
Micrel, Inc.
SY58611U
AC Electrical Characteristics(8)
VCC = +2.5V ±5%, RL = 100Ω across the output pair; Input tr/tf < 300ps, TA = –40°C to +85°C, unless otherwise stated.
Symbol Parameter
Condition
Min Typ Max Units
fMAX Maximum Frequency
NRZ Data
VOUT > 200mV
tPD
Propagation Delay
IN-to-Q VIN: 100mV-200mV
VIN: > 200mV
SEL-to-Q
3.2 Gbps
Clock 2.5
3
GHz
190 330 470 ps
150 280 420 ps
150 450 ps
tSkew
Input-to-Input Skew
Part-to-Part Skew
Note 9, 10
Note 11
5 20 ps
150 ps
tJitter
Data
Random Jitter
Note 12
Deterministic Jitter Note 13
Clock
Cycle-to-Cycle Jitter Note 14
Total Jitter
Note 15
tr, tf Output Rise/Fall Times
(20% to 80%)
At full output swing.
1 psRMS
10 psPP
1 psRMS
10 psPP
40 80 120 ps
Duty Cycle
Differential I/O
47 53 %
Notes:
8. High-frequency AC-parameters are guaranteed by design and characterization.
9. Input-to-Input skew is the time difference between the two inputs and one output, under identical input transitions.
10. Input-to-Input Skew is included in IN-to-Q propagation delay.
11. Part-to-part skew is defined for two parts with identical power supply voltages at the same temperature, same transition edge, and no skew at
the edges at the respective inputs.
12. Random jitter is measured with a K28.7 pattern, measured at ≤ fMAX.
13. Deterministic jitter is measured at 2.5Gbps with both K28.5 and 223–1 PRBS pattern.
14. Cycle-to-cycle jitter definition: the variation period between adjacent cycles over a random sample of adjacent cycle pairs. tJITTER_CC = Tn –Tn+1,
where T is the time between rising edges of the output signal.
15. Total jitter definition: with an ideal clock input frequency of ≤ fMAX (device), no more than one output edge in 1012 output edges will deviate by
more than the specified peak-to-peak jitter value.
March 2007
5 M9999-030607-A
[email protected] or (408) 955-1690
5 Page 
Micrel, Inc.
Input Interface Applications
SY58611U
Figure 4a. CML Interface
(DC-Coupled)
Option: May connect VT to VCC
Figure 4b. CML Interface
(AC-Coupled)
Figure 4c. LVPECL Interface
(DC-Coupled)
Figure 4d. LVPECL Interface
(AC-Coupled)
Figure 4e. LVDS Interface
March 2007
11 M9999-030607-A
[email protected] or (408) 955-1690
11 Page | ||
| Páginas | Total 13 Páginas | |
| PDF Descargar | [ Datasheet SY58611U.PDF ] | |
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