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U6808B Schematic ( PDF Datasheet ) - ATMEL Corporation

Teilenummer U6808B
Beschreibung Specia Fail-safe IC
Hersteller ATMEL Corporation
Logo ATMEL Corporation Logo 




Gesamt 14 Seiten
U6808B Datasheet, Funktion
Features
Digital Self-supervising Watchdog with Hysteresis
One 250-mA Output Driver for Relay
Enable Output Open Collector 8 mA
Over/Undervoltage Detection
ENABLE and RELAY Outputs Protected Against Standard Transients
and 40V Load Dump
ESD Protection According to MIL-STD-883 D Test Method 3015.7
– Human Body Model: ±2 kV (100 pF, 1.5 k)
– Machine Model: ±200 V (200 pF, 0)
1. Description
The U6808B is designed to support the fail-safe function of a safety critical system
(e.g., ABS). It includes a relay driver, a watchdog controlled by an external R/C-net-
work and a reset circuit initiated by an over and undervoltage condition of the 5-V
supply providing a low-level reset signal.
Figure 1-1. Block Diagram
VS
Bandgap
reference
+ 2.44 V
-
+
-
Power-on
reset
Reset
debounce
VS
www.DataSheet4U.com
Reset
delay
RESET
RELAY
Special
Fail-safe IC
U6808B
Under/ overvoltage
detection
RIN
WDI
ENABLE
-
+
Internal
oscillator
Current
limitation
+
-
Watchdog
RC
oscillator
GND
WDC
Rev. 4707B–AUTO–10/05






U6808B Datasheet, Funktion
5.9 Watchdog Window Calculation
5.9.1
Example with Recommended Values
Cosc = 3.3 nF (should be preferably 10%, NPO)
Rosc = 39 k(may be 5%, Rosc < 100 kdue to leakage current and humidity)
5.9.2
RC Oscillator
tWDC(s) = 10-3 × [Cosc (nF) × [(0.00078 × Rosc (k)) + 0.0005]]
fWDC(Hz) = 1/(tWDC)
5.9.3
Watchdog WDI
fWDI(Hz) =0.01 × fWDC
tWDC = 100 µs fWDC = 10 kHz
fWDI = 100 Hz tWDI = 10 ms
5.9.3.1
WDI Pulse Width for Fault Detection after 3 Pulses
Upper watchdog window
Minimum: 169/fWDC = 16.9 ms fWDC/169 = 59.1 Hz
Maximum: 170/fWDC = 17.0 ms fWDC/170 = 58.8 Hz
Lower watchdog window
Minimum: 79/fWDC = 7.9 ms fWDC/79 = 126.6 Hz
Maximum: 80/fWDC = 8.0 ms fWDC/80 = 125.0 Hz
5.9.3.2
WDI Dropouts for Immediate Fault Detection
Minimum: 250/fWDC = 25 ms
Maximum: 251/fWDC = 25.1 ms
Figure 5-3. Watchdog Timing Diagram with Tolerances
Time/s
79/fWDC
80/fWDC
169/fWDC
Watchdog window
update rate is good
170/fWDC
250/fWDC
251/fWDC
Update rate is too
fast
Update rate is
either too fast or
good
Update rate is
either too slow or
good
Update rate is too
slow
Update rate is
either too slow or
pulse has
dropped out
Pulse has
dropped out
5.9.3.3
Reset Delay
The duration of the over or undervoltage pulses determines the enable and reset output. A pulse
duration shorter than the debounce time has no effect on the outputs. A pulse longer than the
debounce time results in the first reset delay. If a pulse appears during this delay, a second
delay time is triggered. Therefore, the total reset delay time can be longer than specified in the
data sheet.
6 U6808B
4707B–AUTO–10/05

6 Page









U6808B pdf, datenblatt
Figure 9-5. Application Circuit
VS = 5 V
100 Hz
µC µC µC
0.01 µF
8765
U6808B
Rosc
39 k
1
Relay
2
V Batt
3
µC
4
Cosc
3.3 nF
12 U6808B
4707B–AUTO–10/05

12 Page





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