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PDF SY58027U Data sheet ( Hoja de datos )
| Número de pieza | SY58027U | |
| Descripción | Ultra Precision Dual 2:1 400mV Lvpecl Mux | |
| Fabricantes | Micrel Semiconductor | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de SY58027U (archivo pdf) en la parte inferior de esta página. Total 10 Páginas | ||
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Micrel
ULTRA PRECISION DUAL 2:1
400mV LVPECL MUX WITH
INTERNAL TERMINATION
Precision Edge™
Precision EdSYg5e8™027U
SY58027U
FEATURES
s Two independent differential 2:1 multiplexers
s Guaranteed AC performance over temperature and
voltage:
Precision Edge™
• DC-to >10.7Gbps data rate throughput
• < 290ps IN-to-Out tpd
• < 80ps tr / tf
s Unique, patent-pending input isolation design
minimizes crosstalk
DESCRIPTION
The SY58027U features two ultra-fast, low jitter 2:1
differential muxes with a guaranteed maximum data
throughput of 10.7Gbps.
s Ultra-low jitter design:
• <1psrms random jitter
• <10pspp deterministic jitter
• <10pspp total jitter (clock)
• <0.7psrms crosstalk-induced jitter
The SY58027U differential inputs include a unique
internal termination design that allows access to the
termination network through a VT pin. The device easily
interfaces to different logic standards, both AC- and DC-
coupled, without external resistor-bias and termination
s Unique, patent-pending 50Ω input termination and
networks. The result is a clean, stub-free, low jitter interface
VT pin accepts DC-coupled and AC-coupled inputs solution. The differential 400mV LVPECL outputs have
(CML, LVDS, PECL)
extremely fast rise/fall times guaranteed to be less than
s 400mV LVPECL output swing
80ps.
s Power supply 2.5V ±5% or 3.3V ±10%
The SY58027U operates from a 2.5V or 3.3V supply and
s –40°C to +85°C temperature range
is guaranteed over the full industrial temperature range
(–40°C to +85°C). The SY58027U is part of Micrel’s Precision
s Available in 32-pin (5mm × 5mm) MLF™ packagewww.DataSheeEt4Ud.cgome™ product family.
APPLICATIONS
All support documentation can be found on Micrel’s web
site at www.micrel.com.
s Data communication systems
s All SONET OC3-OC768 applications
s All Fibre Channel applications
s All GigE applications
FUNCTIONAL BLOCK DIAGRAM
INA0
50Ω
VTA0
50Ω
/INA0
VREF-ACA0
INA1
50Ω
VTA1
50Ω
/INA1
VREF-ACA1
SELA
(TTL/CMOS)
0
MUX A
1S
QA
/QA
INB0
50Ω
VTB0
50Ω
/INB0
VREF-ACB0
INB1
50Ω
VTB1
50Ω
/INB1
VREF-ACB1
SELB
(TTL/CMOS)
AnyGate and Precision Edge are trademarks of Micrel, Inc.
MicroLeadFrame and MLF are trademarks of Amkor Technology, Inc.
M9999-051804
[email protected] or (408) 955-1690
1
0
MUX B
1S
QB
/QB
Rev.: A Amendment: /0
Issue Date: May 2004
1 page  
Micrel
Precision Edge™
SY58027U
AC ELECTRICAL CHARACTERISTICS(7)
VCC = 2.5V ±5% or 3.3V ±10%; TA= –40°C to +85°C; RL = 50Ω to VCC–2V, unless otherwise stated.
Symbol
Parameter
Condition
Min Typ Max Units
fMAX
tpd
Maximum Operating Frequency
Propagation Delay
IN-to-Q
SEL-to-Q
VOUT ≥ 200mV
VIN ≥ 300mV
NRZ Data 10.7
Clock
7
Gbps
GHz
140 215 290
100 220 400
ps
ps
tSKEW
Input-to-Input Skew (Within-bank)
Bank-to-Bank Skew
Note 8
Note 9
6 15 ps
8 20 ps
Part-to-Part Skew
Note 10
100 ps
tJITTER
tr, tf
Data
Random Jitter (RJ)
Deterministic Jitter (DJ)
Clock Cycle-to-Cycle Jitter (RJ)
Total Jitter (TJ)
Crosstalk-Induced Jitter
Channel-to-Channel
Output Rise/Fall Time 20% to 80%
Note 11
Note 12
Note 13
Note 14
Note 15, Within-bank.
At full swing.
1 psrms
10 pspp
1 psrms
10 pspp
0.7 psrms
20 55 80 ps
Notes:
7. High-speed AC parameters are guaranteed by design and characterization. VIN swing ≥ 100mV unless otherwise noted.
8. Input-to-input skew is the difference in time between two inputs to the output within a bank.
9. Bank-to-bank skew is the difference in time from input to the output between bank.
10. Part-to-part skew is defined for two parts with identical power supply voltages at the same temperature and with no skew of the edges at the
respective inputs.
11. Random jitter is measured with a K28.7 comma detect character pattern, measured at 5Gbps and 2.5Gbps/3.2Gbps.
12. Deterministic jitter is measured at 2.5Gbps/3.2Gbps, with both K28.5 and 223–1 PRBS pattern.
13. Cycle-to-cycle jitter definition: the variation of periods between adjacent cycles, Tn–Tn–1 where T is the time between rising edges of the output
signal.
14. Total jitter definition: with an ideal clock input of frequency ≤ fMAX, no more than one output edge in 1012 output edges will deviate by more than the
specified peak-to-peak jitter value.
15. Crosstalk is measured at the output while applying two similar frequencies that are asynchronous with respect to each other at the inputs.
TRUTH TABLES
INA0
0
1
X
X
/INA0
1
0
X
X
INB0
0
1
X
X
/INB0
1
0
X
X
M9999-051804
[email protected] or (408) 955-1690
INA1
X
X
0
1
INB1
X
X
0
1
/INA1
X
X
1
0
/INB1
X
X
1
0
5
SELA
0
0
1
1
SELB
0
0
1
1
QA
0
1
0
1
QB
0
1
0
1
/QA
1
0
1
0
/QB
1
0
1
0
5 Page | ||
| Páginas | Total 10 Páginas | |
| PDF Descargar | [ Datasheet SY58027U.PDF ] | |
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