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PDF SY55856U Data sheet ( Hoja de datos )
| Número de pieza | SY55856U | |
| Descripción | 2.5GHz Precision Two Channel Delay | |
| Fabricantes | Micrel Semiconductor | |
| Logotipo |  |
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Micrel
2.5V/3.3V 2.5GHz
DIFFERENTIAL 2-CHANNEL
PRECISION CML DELAY LINE
SupeSruLSpYite5er5L™8it5e6™U
SY55856U
FINAL
FEATURES
s Guaranteed AC parameters over temp and voltage
• > 2.5GHz FMAX
• < 384ps prop delay
• < 120ps Tr/Tf
s Delay either clock or data
s 50ps increments
s ± 350ps total delay
s Delay either clock or data
s Source terminated CML outputs
s Full differential I/O
s Wide supply voltage spectrum: 2.3V to 3.6V
s Available in a tiny 32-pin EPAD-TQFP package
APPLICATIONS
s Data communications systems
s Telecom systems
SuperLite™
DESCRIPTION
The SY55856U is a 2.5GHz, two-channel, fully differential
CML (Current Mode Logic) delay line. The device is
optimized to adjust the relative delay between two channels,
such as clock and data, in 50ps increments. Both inputs
may be adjusted in either direction in 7 increments of 50ps,
for a total adjustment range of ±350ps. In addition, the
clock input maybe inverted through the CINV control pin.
The SY55856U inputs are designed to accept single-
ended or differential CML signals. The differential CML
outputs are optimized for 50Ω loads (50Ω source terminated),
thus only requires a single 100Ω resistor across the output
pair. Output rise and fall time is an extremely fast 110ps(max)
and the differential swing is 400mV. The maximum
throughput of the SY55856U is guaranteed to exceed
2.5GHz (1.25Gbps).
s High-speed backplanes
s Signal de-skewing
www.DataSheet4U.com
s Pulse alignment
s Digitally controlled delay lines
PIN CONFIGURATION
/DATA_IN
GND
DATA_IN
GND
GND
CLK_IN
GND
/CLK_IN
32 31 30 29 28 27 26 25
1 24
2 23
3 22
4
Top View
21
5 EPAD-TQFP 20
H32-1
6 19
7 18
8 17
9 10 11 12 13 14 15 16
/DATA_OUT
GND
DATA_OUT
GND
GND
CLK_OUT
GND
/CLK_OUT
SuperLite is a trademarks of Micrel, Inc.
PIN NAMES
Pin
CLK_IN,
/CLK_IN
CLK_OUT,
/CLK_OUT
CINV
DATA_IN,
/DATA_IN
DATA_OUT,
/DATA_OUT
LVL
DELAY_SEL
S2, S1, S0
GND
VCC
Function
Differential Clock Input (CML compatible)
Differential Clock Output (CML)
Clock Inversion Control (CML compatible)
Differential Data Input (CML compatible)
Differential Data Output (CML)
Control Level Select (CML compatible)
Delay Path Control (CML compatible)
Delay Selection Control (LSB=S0)
Ground
VCC
Rev.: B Amendment: /0
1 Issue Date: March 2003
1 page  
Micrel
TRUTH TABLES
DATA_IN CLK_IN CINV DATA_OUT /DATA_OUT CLK_OUT /CLK_OUT
0 00
0
1 01
0 01
0
1 10
0 10
0
1 10
0 11
0
1 01
1 00
1
0 01
1 01
1
0 10
1 10
1
0 10
1 11
1
0 01
Table 1. Input to Output Connectivity
SuperLite™
SY55856U
S2 S1 S0 DATA_OUT
CLK_OUT
(CLK_OUT–CLK_IN) –
(D_SEL=0) (ps) (D_SEL=1) (ps) (DATA_OUT–DATA_IN) (ps)
0 00
350
0
–350
0 01
300
50
–250
0 10
250
100
–150
0 11
200
150
–50
1 00
150
200
50
1 01
100
250
150
1 10
50
300
250
1 11
0
350
350
Table 2. Nominal Differential Delay Values
Note 1.
Note 2.
Table 2 defines the approximate relative delay between the two paths. For example, if S2, S1, S0 = 000, and an edge appears at CLK_IN at
the same instant as an edge appears at DATA_IN, then an edge at CLK_OUT will appear about 350ps earlier than an edge at DATA_OUT.
That is, negative values imply CLK_OUT being shifted early with respect to DATA_OUT. Likewise, a positive value in the third column implies
that CLK_OUT is shifted late with respect to DATA_OUT. Please consult the “AC ELECTRICAL CHARACTERISTICS” section for more
precise delay values.
As another example, if an edge at CLK_IN appears 100ps before an edge at DATA_IN, and if S2, S1, S0 = 100, then an edge at CLK_OUT
will appear about 50ps after an edge at DATA_OUT. This setting of the select inputs shifts CLK_IN to CLK_OUT about 150ps later than
DATA_IN to DATA_OUT, moving the timing of the “C” side from 100ps early to 50ps late, as compared with the “D” channel, going through the
part.
5
5 Page | ||
| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet SY55856U.PDF ] | |
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