|
|
PDF NB100EP223 Data sheet ( Hoja de datos )
| Número de pieza | NB100EP223 | |
| Descripción | 1:22 Differential HSTL/PECL to HSTL Clock Driver | |
| Fabricantes | ON Semiconductor | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de NB100EP223 (archivo pdf) en la parte inferior de esta página. Total 10 Páginas | ||
|
No Preview Available !
NB100EP223
3.3V 1:22 Differential
HSTL/PECL to HSTL Clock
Driver with LVTTL Clock
Select and Output Enable
Description
The NB100EP223 is a low skew 1−to−22 differential clock driver,
designed with clock distribution in mind, accepting two clock sources
into an input multiplexer. The part is designed for use in low voltage
applications which require a large number of outputs to drive precisely
aligned low skew signals to their destination. The two clock inputs are
differential HSTL or LVPECL and they are selected by the CLK_SEL
pin which is LVTTL. To avoid generation of a runt clock pulse when
the device is enabled/disabled, the Output Enable (OE), which is
LVTTL, is synchronous ensuring the outputs will only be
enabled/disabled when they are already in LOW state (See Figure 7).
The NB100EP223 guarantees low output−to−output skew. The
optimal design, layout, and processing minimize skew within a device
and from lot to lot. In any differential output pair, the same bias and
termination scheme is required. Unused output pairs should be left
unterminated (open) to “reduce power and switching noise as much as
possible.” Any unused single line of a differential pair should be
terminated the same as the used line to maintain balancewdwwl.DoaatadShseeot4nU.ctohme
differential driver outputs. The output structure uses an open emitter
architecture and will be terminated with 50 W to ground instead of a
standard HSTL configuration (See Figure 6). The wide VIHCMR
specification allows both pair of CLOCK inputs to accept LVDS
levels.
Features
• 100 ps Typical Device−to−Device Skew
• 25 ps Typical Within Device Skew
• HSTL Compatible Outputs Drive 50 W to Ground With No
Offset Voltage
• Maximum Frequency >500 MHz
• 1 ns Typical Propagation Delay
• LVPECL and HSTL Mode Operating Range: VCC = 3 V to 3.6 V
with GND = 0 V, VCCO = 1.6 V to 2.0 V
• Q Output will Default Low with Inputs Open
• Thermally Enhanced 64−Lead LQFP
• CLOCK Inputs are LVDS−Compatible; Requires External 100 W
LVDS Termination Resistor
• Pb−Free Packages are Available*
http://onsemi.com
MARKING
DIAGRAM*
LQFP−64
FA SUFFIX
CASE 848G
NB100
EP223
AWLYYWWG
64
1
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
G = Pb−Free Package
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 8 of this data sheet.
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
© Semiconductor Components Industries, LLC, 2006
November, 2006 − Rev. 7
1
Publication Order Number:
NB100EP223/D
1 page  
NB100EP223
Table 8. AC CHARACTERISTICS VCC = 3.0 V to 3.6 V; VCCO = 1.6 V to 2.0 V; GND = 0 V (Note 4)
0°C 25°C
85°C
Symbol
Characteristic
Min Typ Max Min Typ Max Min Typ Max Unit
VOpp
tPLH
tPHL
Differential Output Voltage
(Figure 3)
fout < 500 MHz
Propagation Delay (Differential)
LVPECL_CLK to Q
HSTL_CLK to Q
600
700
800
750 600
900 1000 750
900 1100 850
750 600 700
900 1100 800 1000 1300
950 1200 850 1050 1350
mV
ps
ps
tskew
Within−Device Skew (Note 5)
Device−to−Device Skew (Note 6)
25 50
100 250
30 65
200 450
50 115
250 450
ps
ps
tJITTER
VPP
Random Clock Jitter (Figure 3) (RMS)
Input Swing (Differential Mode)
(Note 8) (Figure 4)
LVPECL, HSTL
150
0.5 2
800 1200 150
0.5 2
800 1200 150
0.5 2 ps
mV
800 1200
tS OE Set Up Time (Note 7)
tH OE Hold Time
tr/tf Output Rise/Fall Time (20%−80%)
1.0 1.0 1.0
0.5 0.5 0.5
300 450 700 275 450 700 350 500 750
ns
ns
ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
4. Measured with 750 mV (LVPECL) source or 1 V (HSTL) source, 50% duty cycle clock source. All outputs loaded with 50 W to ground
(See Figure 6).
5. Skew is measured between outputs under identical transitions and conditions on any one device.
6. Device−to−Device skew for identical transitions at identical VCC levels.
7. OE Set Up Time is defined with respect to the rising edge of the clock. OE High−to−Low transition ensures outputs remain disabled during
the next clock cycle. OE Low−to−High transition enables normal operation of the next input clock (See Figure 7).
8. VPP is the differential input voltage swing required to maintain AC characteristics including tPD and device−to−device skew.
900
800
700
600
500
400
300
200
0.5
Q AMP (mV)
RMS JITTER (ps)
0.6 0.7 0.8
FREQUENCY (GHz)
0.9
10
9.0
8.0
7.0
6.0
5.0
4.0
3.0
2.0
1.0
0
1.0
Figure 3. Output Frequency (FOUT) versus Output Voltage (VOPP) and Random Clock Jitter (tJITTER)
http://onsemi.com
5
5 Page | ||
| Páginas | Total 10 Páginas | |
| PDF Descargar | [ Datasheet NB100EP223.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| NB100EP223 | 1:22 Differential HSTL/PECL to HSTL Clock Driver | ON Semiconductor |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |