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PDF NTLJD4150P Data sheet ( Hoja de datos )
| Número de pieza | NTLJD4150P | |
| Descripción | Power MOSFET ( Transistor ) | |
| Fabricantes | ON Semiconductor | |
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NTLJD4150P
Power MOSFET
−30 V, −3.4 A, mCoolt Dual P−Channel,
2x2 mm WDFN Package
Features
• WDFN 2x2 mm Package Provides Exposed Drain Pad for
Excellent Thermal Conduction
• Footprint Same as SC−88 Package
• Low Profile (< 0.8 mm) for Easy Fit in Thin Environments
• Bidirectional Current Flow with Common Source Configuration
• This is a Pb−Free Device
Applications
• Li−Ion Battery Charging and Protection Circuits
• LED Backlight, Flashlight
• Dual−High Side Load Switch
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)
Parameter
Symbol Value Unit
Drain−to−Source Voltage
Gate−to−Source Voltage
Continuous Drain Current
(Note 1)
Power Dissipation
(Note 1)
Steady
State
t≤5s
Steady
State
t≤5s
TA = 25°C
TA = 85°C
TA = 25°C
TA = 25°C
VDSS
VGS
ID
PD
−30 V
±20 V
www−.D2a.t7aSheet4UA.com
−2.0
−3.4
1.5 W
2.3
Continuous Drain Current
(Note 2)
Power Dissipation
(Note 2)
Steady
State
TA = 25°C
TA = 85°C
TA = 25°C
ID
PD
−1.8
−1.4
0.7
A
W
Pulsed Drain Current
tp = 10 ms
Operating Junction and Storage Temperature
IDM
TJ,
TSTG
−14
−55 to
150
A
°C
Source Current (Body Diode) (Note 2)
Lead Temperature for Soldering Purposes
(1/8″ from case for 10 s)
IS −1.8 A
TL 260 °C
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. Surface Mounted on FR4 Board using 1 in sq pad size (Cu area = 1.127 in sq
[2 oz] including traces).
2. Surface Mounted on FR4 Board using the minimum recommended pad size.
http://onsemi.com
V(BR)DSS
−30 V
RDS(on) Max
135 mW @ 10 V
200 mW @ 4.5 V
ID Max (Note 1)
−3.4 A
S1 S2
G1 G2
D1 D2
P−CHANNEL MOSFET P−CHANNEL MOSFET
D2 D1
Pin 1
WDFN6
CASE 506AN
MARKING
DIAGRAM
1 JE M G 6
2
3
G
5
4
JE = Specific Device Code
M = Date Code
G = Pb−Free Package
(Note: Microdot may be in either location)
PIN CONNECTIONS
S1 1
D1
6 D1
G1 2
D2 3
D2
5 G2
4 S2
(Top View)
ORDERING INFORMATION
Device
Package
Shipping†
NTLJD4150PTBG WDFN6 3000 / Tape &
(Pb−Free)
Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D
© Semiconductor Components Industries, LLC, 2007
January, 2007 − Rev. 0
1
Publication Order Number:
NTLJD4150P/D
1 page  
NTLJD4150P
TYPICAL PERFORMANCE CURVES (TJ = 25°C unless otherwise noted)
500
400
Ciss
300
VGS = 0 V
TJ = 25°C
200
Coss
100
0 Crss
05
10 15 20 25
DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 7. Capacitance Variation
30
6
5 VDS
QT
20
16
4
QGS
3
2
QGD
VGS 12
8
1
4
ID = −3.0 A
TJ = 25°C
00
0 0.20.40.60.8 1 1.21.41.61.8 2 2.22.42.62.8 3 3.23.43.6
QG, TOTAL GATE CHARGE (nC)
Figure 8. Gate−To−Source and Drain−To−Source
Voltage versus Total Charge
100
VDD = −24 V
ID = −3.0 A
VGS = −4.5 V
tr
td(off)
10 tf
td(on)
4
VGS = 0 V
TJ = 25°C
3
2
1
1
1 10 100
RG, GATE RESISTANCE (OHMS)
Figure 9. Resistive Switching Time
Variation versus Gate Resistance
0
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
−VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS)
Figure 10. Diode Forward Voltage versus Current
10
10 ms
1
*See Note 2 on Page 1
100 ms
1 ms
10 ms
TC = 25°C
0.1 TJ = 150°C
SINGLE PULSE
0.01
0.1
RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT
1
10
dc
100
−VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
http://onsemi.com
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