Datenblatt-pdf.com


VP16256 Schematic ( PDF Datasheet ) - Zarlink Semiconductor

Teilenummer VP16256
Beschreibung Programmable FIR FIlter
Hersteller Zarlink Semiconductor
Logo Zarlink Semiconductor Logo 




Gesamt 19 Seiten
VP16256 Datasheet, Funktion
VP16256
Programmable FIR FIlter
Advance Information
DS4548
ISSUE 4.0
August 1998
The VP16256 contains sixteen multiplier - accumulators, which
can be multi cycled to provide from 16 to 128 stages of digital filtering.
Input data and coefficients are both represented by 16-bit two’s
PIN 1
complement numbers with coefficients converted internally to 12 bits
and the results being accumulated up to 32 bits.
In 16-tap mode the device samples data at the system clock rate
of up to 40MHz. If a lower sample rate is acceptable then the number
of stages can be increased in powers of two up to a maximum of 128.
Each time the number of stages is doubled, the sample clock rate
must be halved with respect to the system clock. With 128 stages the
PIN 1 IDENT
PIN
208
sample clock is therefore one eighth of the system clock.
In all speed modes devices can be cascaded to provide filters of
any length, only limited by the possibility of accumulator overflow. The
32-bit results are passed between cascaded devices without any
intermediate scaling and subsequent loss of precision.
The device can be configured as either one long filter or two
separate filters with half the number of taps in each. Both networks
can have independent inputs and outputs.
Both single and cascaded devices can be operated in decimate-
by-two mode. The output rate is then half the input rate, but twice the
number of stages are possible at a given sample rate. A single device
with a 40MHz clock would then, for example, provide a 128-stage low
pass filter, with a 10MHz input rate and 5MHz output rate.
Coefficients are stored internally and can be down loaded from
GH208
a host system or an EPROM. The latter requires no additional
support, and is used in stand alone applications. A full set of
Pin identification diagram (top view)
coefficients is then automatically loaded at power on, or at the request
See Table 1 for pin descriptions and Table 2 for pinout
of the system. A single EPROM can be used to provide coefficiwewnwt.DsataSheet4U.com
for up to 16 devices.
FEATURES
EPROM
ADDR DATA
CHANGE
COEFF
POWER-ON
RESET
I Sixteen MACs in a Single Device
I Basic Mode is 16-Tap Filter at up to 40MHz
Sample Rates
I Programmable to give up to 128 Taps with
INPUT
DATA
RES
VP
16256
OUTPUT
DATA
EPROM
SCLK
GND
Sampling Rates Proportionally Reducing to 5MHz
I 16-bit Data and 32-bit Accumulators
I Can be configured as One Long Filter or Two Half-
Length Filters
I Decimate-by-two Option will Double the Filter
Length
I Coefficients supplied from a Host System or a local
Fig. 1 A dual filter application
EPROM
I 208-Pin Plastic PowerQuad PQ2 Package
ANALOG
INPUT
EPROM
ADDR DATA
CHANGE
COEFF
POWER-ON
RESET
ADC
RES
COEFFICIENTS
VP
16256
EPROM
OUTPUT
DATA
CLKOP
SCLK GND
Fig. 2 Typical system application
APPLICATIONS
I High Performance Commercial Digital Filters
I Matrix Multiplication
I Correlation
I High Performance Adaptive Filtering
ORDERING INFORMATION
VP16256-27/CG/GH1N 27MHz, Commercial
PowerQuad PQ2 package (GH208)
VP16256-40/CG/GH1N 40MHz, Commercial
PowerQuad PQ2 package (GH208)
plastic
plastic






VP16256 Datasheet, Funktion
VP16256
SPEED MODE 0 (Data input and output at fSCLK) CR14:13 = 00, CR12 = 0. CLKOP held high.
SCLK
FEN
123
16 17 18
31 32 33 34
DA15:0
ABC
35
F31:0
ABC
A′′ B′′ C′′ D′′ E′′
CLKOP
First data point (A)
is read on edge 1
First valid result
including data point (A)
available after edge 16
Valid result contains
the first 16 data points
available after edge 31
SPEED MODE 1 (Data input and output at half fSCLK) CR14:13 = 01, CR12 = 0
SCLK
FEN
123
16 17 18
78 79 80 81 82
DA15:0
AB
F31:0
AB
A′′ B′′ C′′
CLKOP
First data point (A)
is read on edge 1
First valid result
including data point (A)
available after edge 16
Valid result contains
the first 32 data points
available after edge 78
SPEED MODE 2 (Data input and output at a quarter fSCLK) CR14:13 = 10, CR12 = 0
SCLK
FEN
123 4 5
20 21 22 23 24
272 273 274 275 276
DA15:0
AB
F31:0
AB
A′′ B′′
CLKOP
First data point (A)
is read on edge 1
First valid result
including data point (A)
available after edge 20
Valid result contains
the first 64 data points
available after edge 272
SPEED MODE 3 (Data input and output at an eighth fSCLK) CR14:13 = 11, CR12 = 0
SCLK
FEN
1 2 3 4 56 7 8 9
24 25 26 27 28 29 30 31 32
1040 1041 1042 1043
DA15:0 A
B
F31:0
ABA′′
CLKOP
First data point (A)
is read on edge 1
First valid result
including data point (A)
available after edge 24
Valid result contains
the first 128 data points
available after edge 1040
SPEED MODE 1 Decimating (Data input at half fSCLK and output at a quarter fSCLK) CR14:13 = 01, CR12 = 1.
SCLK
FEN
123
18 19 20 21 22
142 143 144 145
DA15:0
AB
F31:0
BB′′
CLKOP
First data point (A)
is read on edge 1
First valid result
including data point (A)
available after edge 18
Valid result contains
the first 64 data points
available after edge 142
Fig. 6 Single Filter timing diagrams
6

6 Page









VP16256 pdf, datenblatt
VP16256
EPROM LSB
ADDRESS
MSB
DATA
A7:0
VP16256
CCS
MASTER
C15:12
C7:0
C11:8
CS
EPROM
BYTE
WEN
(2 SLAVES)
0010
GND
GND
GND
A7:0
VP16256
CCS
SLAVE 1
C15:12
C7:0
C11:8
CS
EPROM
BYTE
WEN
0001
GND
VDD
GND
A7:0
VP16256
CCS
SLAVE 2
C15:12
C7:0
C11:8
CS
EPROM
BYTE
WEN
0010
GND
VDD
GND
Fig. 15 Three device auto EPROM load
When the filter length is less than the maximum, the
VP16256 will only transfer the correct number of coefficients,
and one or more significant address bits will remain low.
Sufficient coefficients are always loaded to allow for a possible
Bank Swap to occur, and the EPROM allocation must allow for
this even if the feature is not to be used. Table 5 shows the
number of coefficients loaded for each of the modes.
If several devices are cascaded, only one device assumes
the role of the Master by having its EPROM pin grounded. It
produces a WEN signal for the other devices, plus four higher
order address outputs on C15:12, see Fig. 14. The extra
address bits on C15:12 define separate areas of EPROM,
containing coefficients for up to fifteen additional devices. The
least significant block of memory must always be allocated to
the Master device. The additional devices need not in practice
be all part of the same cascaded chain, but can consist of
several independent filters. They must, however, all have their
BYTE pins tied low. FRUN can still be used to start these
independent filters after all the devices have been loaded. In
this case, however, each slave FEN pin should be driven by
DFEN from the master device.
When one EPROM is supplying information for several
devices, some means of selectively enabling each additional
device must be provided. This is achieved by using the C11:8
pins on the slave devices as binary coded inputs to define one
to fifteen extra devices. These coded inputs always
correspond to the block address used for the segment of
EPROM allocated to that device. Code ‘all zeros’ must not be
used since the Master device has implied use of the bottom
segment. This is necessary since the C11:8 pins are
alternatively used on the Master device to define the number
of devices supported by the EPROM.
In addition to providing the most significant addresses to
the EPROM, the C15:12 address outputs from the master
device must also drive the C15:12 inputs on the slave devices.
These C15:12 inputs are internally compared to the C11:8
inputs to decide if that device is currently to be loaded. This
approach avoids the need for external decoders and makes
the CS input redundant. This input, however, must be tied low
on every device in an EPROM supported system.
The Control Coefficient pin (CCS) is used to define when
the control register is to be loaded. It becomes an output on the
Master device which provides an EPROM address bit next in
significance above A7:0, and also drives the CCS inputs on the
slave devices. This output is high for the first two EPROM
transfers in order to access the control information, and then
remains low whilst the coefficients are loaded. This control
information is thus not stored adjacent to the coefficients within
the EPROM, and in fact the EPROM must provide twice the
storage necessary to contain the coefficients alone. All but two
of the bytes in the additional half are redundant. See Fig.16 for
the EPROM memory map.
12

12 Page





SeitenGesamt 19 Seiten
PDF Download[ VP16256 Schematic.PDF ]

Link teilen




Besondere Datenblatt

TeilenummerBeschreibungHersteller
VP16256Programmable FIR FilterMitel Networks Corporation
Mitel Networks Corporation
VP16256Programmable FIR FIlterZarlink Semiconductor
Zarlink Semiconductor
VP16256-27Programmable FIR FilterMitel Networks Corporation
Mitel Networks Corporation
VP16256-27CGProgrammable FIR FilterMitel Networks Corporation
Mitel Networks Corporation
VP16256-27CGGH1NProgrammable FIR FilterMitel Networks Corporation
Mitel Networks Corporation

TeilenummerBeschreibungHersteller
CD40175BC

Hex D-Type Flip-Flop / Quad D-Type Flip-Flop.

Fairchild Semiconductor
Fairchild Semiconductor
KTD1146

EPITAXIAL PLANAR NPN TRANSISTOR.

KEC
KEC


www.Datenblatt-PDF.com       |      2020       |      Kontakt     |      Suche