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NJ88C50 Schematic ( PDF Datasheet ) - Zarlink Semiconductor

Teilenummer NJ88C50
Beschreibung Dual Low Power Frequency Synthesiser
Hersteller Zarlink Semiconductor
Logo Zarlink Semiconductor Logo 




Gesamt 17 Seiten
NJ88C50 Datasheet, Funktion
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NJ88C50
Dual Low Power Frequency Synthesiser
The NJ88C50 is a low power integrated circuit, designed
as the heart of a fast locking PLL subsystem in a mobile radio
application. It is manufactured on Mitel Semiconductor 1.4
micron double polysilicon CMOS process, which ensures that
low power and low noise performance is achieved. The device
contains two synthesisers, one for the generation of VHF
signals up to 125MHz and a second for UHF (when used with
a mulitmodulus prescaler such as the SP8713/14/15). The
main synthesiser has the capability of driving a dual speed
loop filter and also can perform Fractional-N interpolation.
Both synthesisers use current source outputs from their
phase detectors to minimise external components. Various
sections may be powered down for battery economy.
FEATURES
• 30MHz main synthesiser
• 125MHz auxiliary synthesiser
• Programmable output current
from phase detector - up to 10mA
• High input sensitivity
• Fractional-N interpolator
• Supports up to 4 modulus prescalers
• SSOP package
DS3805
ISSUE 1.8
Ordering Information
NJ88C50/MA/NP - (Industrial temp
range in SSOP package)
June 2002
AVDD
FIM
FIMB
DATA
CKIN
STROBE
RI
FIA
RSA
PDA
1 20
2 19
3 18
4 17
5 NJ88C50 16
6 15
7 14
8 13
9 12
10 11
AGND
MOD2
MOD1
SCREEN
RSC
RSM
VDD
PDP
GND
PDI
APPLICATIONS
• NMT, AMPS, ETACS cellular
• GSM, IS-54, RCR-27 cellular
• DCS1800 microcellular
• DLMR, DSRR, TETRA
• DECT, PHP cordless telephones
NP20
Figure 1 - Pin assignment
ABSOLUTE MAXIMUM RATINGS
Storage temperature
-55°C to +150°C
Operating temperature
-40°C to +85°C
Supply voltage
-0.5 to 7.0V
Voltage on any pin
-0.3V to (VDD + 0.3V)
FIM
FIMB
DATA
CKIN
STROBE
RI
FIA
MOD1
MOD2
MAIN N
BUFFER
SERIAL
INPUT
REGISTER
R BUFFER
AUX. N
BUFFER
MAIN N-DIVIDER
LATCH
LATCH
R DIVIDER
QBAR
Q
LATCH
AUX. N-DIVIDER
PHASE
DETECTOR
RSC RSM
CURRENT
SOURCE
PDI
PDP
LATCH
FRACTIONAL-N
SYSTEM
PHASE
DETECTOR
CURRENT
SOURCE
PDA
Figure 2 - Simplified block diagram
RSA






NJ88C50 Datasheet, Funktion
NJ88C50
However the alternation between the N and N+1 values
causes a ripple in the output frequency. This ripple is not
desirable in radio frequency synthesisers. This ripple or jitter
waveform is predictable from the pattern of N and N+1 values
and so can be cancelled.
The instantaneous accumulator value, A, is proportional to
the cumulative frequency error caused by ignoring the
fractional part during the periods of the divide by N. The
accumulator value, A, may therefore be used to generate a
waveform corresponding to the jitter waveform, that is then
used to cancel the jitter out of the phase detector. This jitter
compensation current pulse is equal to A.Icomp where Icomp
represents the step size as A is incremented.
Corresponding to the two alternative values of Iprop,
Iprop(0) and Iprop(1), Icomp will take the values Icomp(0) and
Icomp(1). Icomp is always pull-up, and the magnitude of its
steps for perfect jitter compensation are related to the value
of Iprop by the factors
0 , 1/Q.Ntot , 2/Q.Ntot , 3/Q.Ntot ........ Q-1/Q.Ntot
where Q = accumulator modulus in use (5 or 8)
Since
Iprop(0) = CN.Ibo
and CN is an approximation to Ntot apart from a scaling factor,
the value of Icomp(0) required becomes independent of Ntot
and its steps are
0 , 1/Q , 2/Q , 3/Q ........ Q-1/Q times Ibo.(scaling factor)
where scaling factor = Max. value of CN to be used
Corresponding max. value of Ntot
therefore
Ico = 1 x CN(max) x Ibo
Q Ntot(max)
and Icomp(0) = A.Ico
where Ico is scaled from the external current setting resistor
RSC.
Ico = Irsc/128.
Typically Ntot(max) might be 10000, with CN(max)=250
and Q=8, so the current step will be of magnitude Ibo/320.
Since Ibo is only 1 uA, this is a very small value; however this
value only applies if Icomp is a continuous current. Icomp
however will be a short current pulse coincident with the Iprop
pulse, in order to cancel jitter components over the widest
possible frequency range.
When the duty factor of Icomp is taken into account, its pulse
value may be increased accordingly. Icomp is therefore
generated as a pulse of fixed width equal to two periods of the
input reference clock frequency, with a timing that straddles
the active edge of the reference divider output pulse supplied
to the main phase detector, as shown below: (Fig 6).
Since the duty factor of Icomp is 2/M and depends on the
value of M programmed, it is possible to set the peak pulse
value of Icomp(0) by means of the external current setting
resistor RSC to correspond with the value of M intended, the
value of scaling factordefined above, the accumulator
modulus Q and the value of Ibo set by the other current setting
resistor.
therefore Ico = 1 x Nmax x M x Ibo
Q Ntot(max) 2
This gives a typical value for Ico of 0.1µA.
The two values of Icomp, Icomp(0) and Icomp(1) are related
by
Icomp(1) = 2L+1 .Icomp(0)
Icomp(0) occuring when the strobe line is low and Icomp(1)
occuring when the strobe line is high loading either WORDA
or WORDA2 (see programming section, page 8 and 9) .
Corresponding to the pull-up pulse Icomp(1) that is added
to the proportional charge pump pulse Iprop(1), there is also
a pull-up current pulse Icomp2 which is added to the integral
charge pump pulse Iint. This pulse Icomp2 only applies when
the stobe line is high (loading either WORDA or WORDA2).
When the strobe line is low there will be no Iint or Icomp2
pulses. The value of Icomp2 is given by
Icomp2 = Icomp(1).K
where K is a four bit number entered as part of the serial
programming data.
M cycles of the reference input frequency
Active edge
Reference to phase detector
Timing of Icomp pulse
2 reference frequency cycles
Figure 6
6

6 Page









NJ88C50 pdf, datenblatt
NJ88C50
DYNAMIC
Vdd = 5V, Tamb = -40 to +85°C
Output signals - Main synthesiser, integral output
Parameter
Min Typ Max Unit Condition
Output signal - PDI
IINT Up
(1mA - 5mA) see notes 1&2
IINT Down
(1mA - 5mA) see notes 1&2
IINT Up
(5mA - 10mA) see notes 1&2
IINT Down
(5mA - 10mA) see notes 1&2
-10% +Ibo.CN.2L+1.K
+10% mA
0<VPD<4.45V, Strobe=5V
-10% -Ibo.CN.2L+1.K
+10% mA 0.35<VPD<5V, Strobe=5V
-10% +Ibo.CN.2L+1.K
+10% mA
0<VPD<4.3V, Strobe=5V
-10% -Ibo.CN.2L+1.K
+10% mA 0.5<VPD<5V, Strobe=5V
Tristate
50 nA
Notes
1. The typical value of IINT is set by the value of Iprop(1) and the programmed value of K.
2. The current output IINT is specified between 1mA and 10mA.
DYNAMIC
Vdd = 5V, Tamb = -40 to +85°C
Output signals - Main synthesiser, under Fractional-N control
Parameter
Min Typ Max Unit Condition
Output signal - PDP
ICOMP(0)
see notes 1&3
-10%
Ico.Acc.
+10% µA
0<VPD<4.55V, Strobe=0V
ICOMP (1)
see notes 2&3
-10%
Ico.Acc.2L+1.
+10% µA
0<VPD<4.55V, Strobe=5V
Output signal - PDI
ICOMP2
see notes 4&5
-10%
Ico.Acc.2L+1.K
+10%
µA
0<VPD<4.55V, Strobe=5V
Notes
1. The typical value of ICOMP(0) is set by the fractional-N accumulator value Acc and the current Irsc set by the external
resistor RSC, where Ico=Irsc /128. Irsc is typically 12.8µA.
2. The typical value of ICOMP(1) is set by the value of ICOMP(0) and the programmed value of L.
3. The current output ICOMP is specified up to 12µA.
4. The typical value of ICOMP2 is set by the value of ICOMP(1) and the programmed value of K.
5. The current output ICOMP2 is specified up to 180µA.
12

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