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PDF MV1403 Data sheet ( Hoja de datos )
| Número de pieza | MV1403 | |
| Descripción | PCM MACROCELL DEMONSTRATOR | |
| Fabricantes | Zarlink Semiconductor | |
| Logotipo |  |
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MV1403
CLK
FRS
TZS
D1
Q
CLK
FRS
TZS
D1
D3N-8N
Q
d1
d1 0 0
11
011
Macrocell transmitting timeslot zero sync. word
d1
d3-d8
d1
1 d3 d4 d5 d6 d7 d8
Macrocell transmitting timeslot zero non-sync. word
Figure 3: Timeslot zero transmitter timing
CLK
1 32 64 96 128
FRS
D D5 D6 D7
D8 D1
TS16
Q D1 D2 D3 D4 D5 D6 D7 D8
N.B. The D input is sampled on counts 24, 56, 88 etc.
Figure 4: Timeslot sixteen transmitter timing
CLK
D
Q
TXD2
BB
B
TXD1
BB
V
NOTES:
1. B is a mark, V is an HDB3 violation.
2. There is a 3 clock period delay from input (D) to output (TXD1/2)
3. This diagram assumes the last preceding violation occurred on TXD1.
4 Figure 5: HDB3 encoder timing
V
5 Page 
MV1403
PIN DESCRIPTIONS
Symbol Pin No.
VDD1
ER
DP48 HP44
22
Mode
name
(see note 1)
GLOBAL
RX
MFQ1 3 3 RX
TX
MFQ2 4 4 RX
TX
DQ8 5 5 RX
DQ7 6
6
DQ6 7
7
DQ5 8
8
DQ4 9
9
DQ3 10
10
TX
DQ1 11 11 RX
TX1
.
TX2
Q1S 12 12 RX
VDD2
13
-
GLOBAL
GND1 14 13 GLOBAL
LIA 15 14 RX
Pin name and description
Digital supply voltage. 5V (Note 2)
Timeslot Zero Receiver (RXTSZ) Macrocell - Sync Word Error Output (ER).
This flag goes high for one frame immediately after detection of a bad timeslot
zero sync word, whilst the macrocell is in sync. Three consecutive errors of
this type will put the receiver out of sync. The last ER pulse of this sequence
will be longer than 256 periods if a valid sync word is detected during the pulse.
Timeslot Zero Receiver (RXTSZ) Macrocell - Synchronisation Alarm Output
(SA). This error flag goes high when the macrocell is out of sync and only
changes state at the end of a sync frame timeslot zero.
Timeslot Zero Transmitter (TXTSZ) Macrocell - Timeslot Zero Sync frame
marker (TZS). This output is high during timeslot zero of sync frames and
changes state at the beginning of timeslot one, bit 2 of every frame.
Timeslot Zero Receiver (RXTSZ) Macrocell - Remote Alarm Indication Output
(RAI) This is a persistence checked version of the Q3N output. When
RXTSZ is in sync, this output goes high if the current and previous timeslot
zero bit 3 of non-sync frames are both high. This output changes state at bit 1,
timeslot 1 of non-sync frames. When the macrocell is out of sync this output is
forced low in the non-sync frame following the last bad sync frame, and is
held low until the macrocell comes back into sync.
Timeslot Zero Transmitter (TXTSZ) Macrocell - Data Output (Q). The sync
word and signalling data word appear here in 8 bit bursts during timeslot zero.
Bit 1 appears immediately after the rising edges of CLK and FRS. This output
is low during all timeslots except timeslot zero.
Timeslot Zero Receiver (RXTSZ) Macrocell - Data Outputs (Q8N-Q3N). These
outputs are extracted from bits 8-3 of timeslot zero during non-sync frames
respectively. These outputs change at the start of bit 1, timeslot 1 of non-sync
frames .
Timeslot Zero Transmitter (TXTSZ) Macrocell Data Inputs (D8N-D3N). These
data inputs are inserted into bits 8-3 of timeslot zero during non-sync frames
respectively. This data must be set up prior to the rising edge of FRS.
Timeslot Zero Receiver (RXTSZ) Macrocell - Data Output (Q1 N). With
CRC = 0, this output latches data from bit I, timeslot zero of non-sync frames.
The output changes at the beginning of bit l, timeslot 1 of non-sync frames.
With CRC=1, this output latches data from bit 1 of frame 15 of the CRC
multiframe.
Timeslot Zero Transmitter (TXTSZ) Macrocell - Data Input (D1). The data on
this pin is inserted into the International spare bit (bit 1, timeslot zero of both
sync and non-sync frames), and must be set up prior to the rising edge of
FRS.
This pin is unused since the Dl input of the Timeslot Zero Transmitter is
connected internally to the Q output of the CRC Generator.
Timeslot Zero Receiver (RXTSZ) Macrocell - Data Output (Q1S). With
CRC = 0, this output latches data from bit 1, timeslot zero of sync frames. The
output changes at the beginning of bit 1, timeslot 1 of sync frames. With
CRC = 1, this output latches data from bit 1 of frame 13 of the CRC multiframe.
Digital supply voltage. 5V (Note 2)
Digital ground. 0V (Note 2)
HDB3 Decoder (HDB3DC) Macrocell - Loss of Input Alarm Output (LIA). This
alarm output goes high after 11 consecutive zeros have been detected on the
HDB3 inputs. It is reset on detection of a mark (1) on either HDB3 input.
10
11 Page | ||
| Páginas | Total 18 Páginas | |
| PDF Descargar | [ Datasheet MV1403.PDF ] | |
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