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PDF MMDF2C03HD Data sheet ( Hoja de datos )
| Número de pieza | MMDF2C03HD | |
| Descripción | Power MOSFET ( Transistor ) | |
| Fabricantes | ON Semiconductor | |
| Logotipo |  |
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MMDF2C03HD
Preferred Device
Power MOSFET
2 Amps, 30 Volts
Complementary SO−8, Dual
These miniature surface mount MOSFETs feature ultra low RDS(on)
and true logic level performance. They are capable of withstanding
high energy in the avalanche and commutation modes and the
drain-to-source diode has a very low reverse recovery time.
MiniMOSt devices are designed for use in low voltage, high speed
switching applications where power efficiency is important. Typical
applications are dc-dc converters, and power management in portable
and battery powered products such as computers, printers, cellular and
cordless phones. They can also be used for low voltage motor controls
in mass storage products such as disk drives and tape drives. The
avalanche energy is specified to eliminate the guesswork in designs
where inductive loads are switched and offer additional safety margin
against unexpected voltage transients.
Features
• Ultra Low RDS(on) Provides Higher Efficiency and Extends Battery Life
• Logic Level Gate Drive − Can Be Driven by Logic ICs
• Miniature SO-8 Surface Mount Package − Saves Board Space
• Diode Is Characterized for Use In Bridge Circuits
• Diode Exhibits High Speed, With Soft Recovery
• IDSS Specified at Elevated Temperature
• Avalanche Energy Specified
• Mounting Information for SO-8 Package Provided
• Pb−Free Package is Available
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted) (Note 1)
Rating
Symbol Value Unit
Drain−to−Source Voltage
Gate−to−Source Voltage
Drain Current − Continuous
Drain Current − Pulsed
N−Channel
P−Channel
N−Channel
P−Channel
VDSS
VGS
ID
IDM
30 Vdc
± 20 Vdc
4.1 A
3.0
21
15
Operating and Storage Temperature Range
Total Power Dissipation @ TA= 25°C (Note 2)
Thermal Resistance, Junction−to−Ambient
(Note 2)
TJ, Tstg
PD
RqJA
− 55 to 150
2.0
62.5
°C
W
°C/W
Single Pulse Drain−to−Source Avalanche
Energy − Starting TJ = 25°C
(VDD = 30 V, VGS = 5.0 V, Peak IL = 9.0 Apk,
L = 8.0 mH, RG = 25 W)
N−Channel
(VDD = 30 V, VGS = 5.0 V, Peak IL = 6.0 Apk,
L = 18 mH, RG = 25 W)
P−Channel
Max Lead Temperature for Soldering, 0.0625″
from case. Time in Solder Bath is 10 seconds
EAS
TL
mJ
324
324
260 °C
Maximum ratings are those values beyond which device damage can occur.
Maximum ratings applied to the device are individual stress limit values (not
normal operating conditions) and are not valid simultaneously. If these limits are
exceeded, device functional operation is not implied, damage may occur and
reliability may be affected.
1. Negative signs for P−Channel device omitted for clarity.
2. Mounted on 2” square FR4 board (1” sq. 2 oz. Cu 0.06” thick single sided) with
one die operating, 10 sec. max.
© Semiconductor Components Industries, LLC, 2006
February, 2006 − Rev. 7
1
http://onsemi.com
2 AMPERES, 30 VOLTS
RDS(on) = 70 mW (N-Channel)
RDS(on) = 200 mW (P-Channel)
N−Channel
D
P−Channel
D
GG
SS
MARKING
DIAGRAM
8
1
SO−8
CASE 751
STYLE 14
8
D2C03
AYWWG
G
1
D2C03 = Device Code
A = Assembly Location
Y = Year
WW = Work Week
G = Pb−Free Package
(Note: Microdot may be in either location)
PIN ASSIGNMENT
N−Source
N−Gate
P−Source
P−Gate
1 8 N−Drain
2 7 N−Drain
3 6 P−Drain
4 5 P−Drain
ORDERING INFORMATION
Device
Package
Shipping†
MMDF2C03HDR2 SO−8 2500 Tape & Reel
MMDF2C03HDR2G SO−8 2500 Tape & Reel
(Pb−Free)
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
Preferred devices are recommended choices for future use
and best overall value.
Publication Order Number:
MMDF2C03HD/D
1 page  
100
VGS = 0 V
10
MMDF2C03HD
TYPICAL ELECTRICAL CHARACTERISTICS
N−Channel
P−Channel
1000
VGS = 0 V
TJ = 125°C
100°C
100 TJ = 125°C
100°C
1
0 5 10 15 20 25 30
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 6. Drain−To−Source Leakage
Current versus Voltage
10
0 5 10 15 20 25 30
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 6. Drain−To−Source Leakage
Current versus Voltage
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge
controlled. The lengths of various switching intervals (Dt)
are determined by how fast the FET input capacitance can
be charged by current from the generator.
The published capacitance data is difficult to use for
calculating rise and fall because drain−gate capacitance
varies greatly with applied voltage. Accordingly, gate
charge data is used. In most cases, a satisfactory estimate of
average input current (IG(AV)) can be made from a
rudimentary analysis of the drive circuit so that
t = Q/IG(AV)
During the rise and fall time interval when switching a
resistive load, VGS remains virtually constant at a level
known as the plateau voltage, VSGP. Therefore, rise and fall
times may be approximated by the following:
tr = Q2 x RG/(VGG − VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turn−on and turn−off delay times, gate current
is not constant. The simplest calculation uses appropriate
values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG − VGSP)]
td(off) = RG Ciss In (VGG/VGSP)
The capacitance (Ciss) is read from the capacitance curve
at a voltage corresponding to the off−state condition when
calculating td(on) and is read at a voltage corresponding to the
on−state when calculating td(off).
At high switching speeds, parasitic circuit elements
complicate the analysis. The inductance of the MOSFET
source lead, inside the package and in the circuit wiring
which is common to both the drain and gate current paths,
produces a voltage at the source which reduces the gate drive
current. The voltage is determined by Ldi/dt, but since di/dt
is a function of drain current, the mathematical solution is
complex. The MOSFET output capacitance also
complicates the mathematics. And finally, MOSFETs have
finite internal gate resistance which effectively adds to the
resistance of the driving source, but the internal resistance
is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate
resistance (Figure 9) shows how typical switching
performance is affected by the parasitic circuit elements. If
the parasitics were not present, the slope of the curves would
maintain a value of unity regardless of the switching speed.
The circuit used to obtain the data is constructed to minimize
common inductance in the drain and gate circuit loops and
is believed readily achievable with board mounted
components. Most power electronic loads are inductive; the
data in the figure is taken with a resistive load, which
approximates an optimally snubbed inductive load. Power
MOSFETs may be safely operated into an inductive load;
however, snubbing reduces switching losses.
http://onsemi.com
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