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PDF MB82DP02183D Data sheet ( Hoja de datos )
| Número de pieza | MB82DP02183D | |
| Descripción | 32M Bit (2 M word X 16 bit) Mobile Phone Application Specific Memory | |
| Fabricantes | Fujitsu Media Devices | |
| Logotipo |  |
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FUJITSU SEMICONDUCTOR
DATA SHEET
DS05-11436-1E
MEMORY Mobile FCRAMTM
CMOS
32M Bit (2 M word × 16 bit)
Mobile Phone Application Specific Memory
MB82DP02183D-65L
■ DESCRIPTION
CMOS 2,097,152-WORD x 16 BIT
Fast Cycle Random Access Memory
with Low Power SRAM Interface
The Fujitsu MB82DP02183D is a CMOS Fast Cycle Random Access Memory (FCRAM*) with asynchronous
Static Random Access Memory (SRAM) interface containing 33,554,432 storages accessible in a 16-bit format.
MB82DP02183D is utilized using a Fujitsu advanced FCRAM core technology and improved integration in com-
parison to regular SRAM.
This MB82DP02183D is suited for mobile applications such as Cellular Handset and PDA.
*: FCRAM is a trademark of Fujitsu Limited, Japan
■ FEATURES
• Asynchronous SRAM Interface
• Fast Access Cycle Time
: tAA = tCE = 65 ns Max
• 8 words Page Access Capability : tPAA = 20 ns Max
• Low Voltage Operating Condition : VDD = + 2.6 V to + 3.5 V
• Wide Operating Temperature : TA = − 30 °C to + 85 °C
TJ = − 30 °C to + 90 °C
• Byte Control by LB and UB
• Low Power Consumption
: IDDA1 = 30 mA Max
IDDS1 = 100 µA Max
• Various Power Down mode
: Sleep
4M-bit Partial
8M-bit Partial
• Shipping Form
: Wafer/Chip
Copyright©2006 FUJITSU LIMITED All rights reserved
1 page  
MB82DP02183D-65L
■ POWER DOWN
Power Down
The Power Down is low power idle state controlled by CE2. CE2 Low drives the device in power down mode
and maintains low power idle state as long as CE2 is kept Low. CE2 High resumes the device from power down
mode.
This device has three power down modes, Sleep, 4M-bit Partial and 8M-bit Partial. The selection of power down
mode can be programmed by series of read/write operation. Each mode has following data retention features.
Mode
Data Retention
Retention Address
Sleep (default)
No
N/A
4M-bit Partial
4M bits
00000h to 3FFFFh
8M-bit Partial
8M bits
00000h to 7FFFFh
The default state is Sleep and it is the lowest power consumption but all data will be lost once CE2 is brought
to Low for Power Down. It is not required to program to Sleep mode after power-up.
Power Down Program Sequence
The program requires total six read/write operations with unique address. Between each read/write operation
requires that device be in standby mode. Following table shows the detail sequence.
Cycle #
Operation
Address
Data
1st
Read
1FFFFFh (MSB)
Read Data (RDa)
2nd Write
1FFFFFh
RDa
3rd Write
1FFFFFh
RDa
4th Write
1FFFFFh
Don’t care (X)
5th Write
1FFFFFh
X
6th Read
Address Key
Read Data (RDb)
The first cycle is to read from most significant address (MSB).
The second and third cycles are to write to MSB. If the second or third cycle is written into the different address,
the program is cancelled and the data written by the second or third cycle is valid as a normal write operation.
It is recommended to write back the data (RDa) read by first cycle to MSB in order to secure the data.
The forth and fifth cycle is to write to MSB. The data of forth and fifth cycle are don’t-care. If the forth or fifth
cycle is written into different address, the program is also cancelled but write data may not be written as normal
write operation.
The last cycle is to read from a specific address key for power down mode selection. And read data (RDb) is invalid.
Once this program sequence is performed from a Partial mode to the other Partial mode, the written data stored
in a memory cell array may be lost. So, it should perform this program prior to regular read/write operation if
Partial power down mode is used.
Address Key
The address key has following format.
Mode
Sleep (default)
4M-bit Partial
8M-bit Partial
A20
1
1
0
Address
A19 A18 to A0
11
01
11
Hexadecimal
1FFFFFh
17FFFFh
0FFFFFh
5
5 Page 
MB82DP02183D-65L
(5) AC TEST CONDITIONS
Description
Input High Level
Input Low Level
Input Timing Measurement Level
Input Transition Time
(At recommended operating conditions unless otherwise noted.)
Symbol
Test Setup
Value
Unit
Note
VIH
⎯
VDD × 0.8
V
VIL
⎯
VDD × 0.2
V
VREF
⎯
VDD × 0.5
V
tT Between VIL and VIH
5
ns
• AC MEASUREMENT OUTPUT LOAD CIRCUIT
VDD
0.1 µF
VSS
Device under
Test
Output
50 pF
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet MB82DP02183D.PDF ] | |
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