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PDF MB82DBS04163C Data sheet ( Hoja de datos )
| Número de pieza | MB82DBS04163C | |
| Descripción | MEMORY Mobile FCRAMTM CMOS 64 M Bit | |
| Fabricantes | Fujitsu Media Devices | |
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FUJITSU SEMICONDUCTOR
DATA SHEET
DS05-11432-1E
MEMORY Mobile FCRAMTM
CMOS
64 M Bit (4 M word×16 bit)
Mobile Phone Application Specific Memory
MB82DBS04163C-70L
■ DESCRIPTION
The FUJITSU MB82DBS04163C is a CMOS Fast Cycle Random Access Memory (FCRAM*) with asynchronous
Static Random Access Memory (SRAM) interface containing 67,108,864 storages accessible in a 16-bit format.
MB82DBS04163C is utilized using a FUJITSU advanced FCRAM core technology and improved integration in
comparison to regular SRAM.
The MB82DBS04163C adopts asynchronous page mode and synchronous burst mode for fast memory access
as user configurable options.
This MB82DBS04163C is suited for mobile applications such as Cellular Handset and PDA.
* : FCRAM is a trademark of FUJITSU LIMITED, Japan
■ PRODUCT LINEUP
Parameter
Access Time (Max) (tCE, tAA)
Access Time from CLK (Max) (tAC)
Active Current (Max) (IDDA1)
Standby Current (Max) (IDDS1)
Power Down Current (Max) (IDDPS)
RL = 6, 5
TA ≤ + 40 °C
MB82DBS04163C-70L
70 ns
10 ns
35 mA
90 µA
10 µA
■ FEATURES
• Asynchronous SRAM Interface
• Fast Access Time : tCE = 70 ns Max
• 8 words Page Access Capability : tPAA = 20 ns Max
• Burst Read/Write Access Capability : tAC = 10 ns Max
• Low Voltage Operating Condition : VDD = 1.7 V to 1.95 V
• Wide Operating Temperature : TA = -30 °C to +85 °C
• Byte Control by LB and UB
• Low-Power Consumption : IDDA1 = 35 mA Max
IDDS1 = 90 µA Max (TA ≤ + 40°C )
• Various Power Down mode : Sleep
8 M-bit Partial
16 M-bit Partial
• Shipping Form : Wafer/Chip
1 page  
MB82DBS04163C-70L
■ STATE DIAGRAM
• Initial/Standby State
Power
Up
Pause Time
Power
Down CE2 = H
CE2 = L Standby
CR Set
@M = 1 @M = 0
CE2 = H
@RP = 0
Asynchronous Operation
(Page Mode)
Synchronous Operation
(Burst Mode)
Common State
CE2 = H
@RP = 1
Power
Down
Standby CE2 = L
• Asynchronous Operation
CE2 = CE1 = H
Standby
Byte
Control
CE1 = L &
WE = L
CE1 = L
CE1 = H
CE1 = L &
OE = L
CE1 = H
Output
Disable
CE1 = H
WE = H
WE = L
OE = H
OE = L
Write
Byte Control @OE = L
Read
Address Change
or Byte Control
• Synchronous Operation
CE1 = H
CE2 = CE1 = H
Standby
CE1 = H
Write
Suspend
WE = L
CE1 = H
WE = H
CE1 = L,
ADV Low Pulse,
& WE = L
CE1 = H
CE1 = L,
ADV Low Pulse,
& OE = L
OE = H
Read
Suspend
OE = L
ADV Low Pulse
Write
ADV Low Pulse
(@BL = 8 or 16, and after burst
operation is completed)
Read
ADV Low Pulse
Note : Assuming all the parameters specified in AC CHARACTERISTICS are satisfied. Refer to the "■FUNCTIONAL
DESCRIPTION", "2. AC Characteristics" in "■ELECTRICAL CHARACTERISTICS", and "■TIMING DIA-
GRAMS" for details.
5
5 Page 
MB82DBS04163C-70L
CLK
Address
ADV
CE1
OE or WE
DQ [Output]
WAIT
DQ [Input]
WAIT
DQ [Output]
WAIT
DQ [Input]
WAIT
DQ [Output]
WAIT
DQ [Input]
WAIT
DQ [Output]
WAIT
DQ [Input]
WAIT
012 3 45 6
Valid address
RL = 3
High-Z
High-Z
RL = 4
High-Z
High-Z
RL = 5
High-Z
High-Z
RL = 6
High-Z
High-Z
Q1 Q2 Q3 Q4 Q5
D1 D2 D3 D4 D5 D6
Q1 Q2 Q3 Q4
D1 D2 D3 D4 D5
Q1 Q2 Q3
D1 D2 D3 D4
Q1 Q2
D1 D2 D3
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet MB82DBS04163C.PDF ] | |
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