Datenblatt-pdf.com


FIN3383 Schematic ( PDF Datasheet ) - Fairchild Semiconductor

Teilenummer FIN3383
Beschreibung (FIN3383 - FIN3386) Low Voltage 28-Bit Flat Panel Display Link Serializers/Deserializers
Hersteller Fairchild Semiconductor
Logo Fairchild Semiconductor Logo 




Gesamt 18 Seiten
FIN3383 Datasheet, Funktion
www.DataSheet4U.com
October 2003
Revised April 2005
FIN3385 FIN3383
FIN3384 FIN3386
Low Voltage 28-Bit Flat Panel Display Link
Serializers/Deserializers
General Description
The FIN3385 and FIN3383 transform 28 bit wide parallel
LVTTL (Low Voltage TTL) data into 4 serial LVDS (Low
Voltage Differential Signaling) data streams. A phase-
locked transmit clock is transmitted in parallel with the data
stream over a separate LVDS link. Every cycle of transmit
clock 28 bits of input LVTTL data are sampled and trans-
mitted.
The FIN3386 and FIN3384 receive and convert the 4/3
serial LVDS data streams back into 28/21 bits of LVTTL
data. Refer to Table 1 for a matrix summary of the Serializ-
ers and Deserializers available. For the FIN3385, at a
transmit clock frequency of 85MHz, 28 bits of LVTTL data
are transmitted at a rate of 595Mbps per LVDS channel.
These chipsets are an ideal solution to solve EMI and cable
size problems associated with wide and high-speed TTL
interfaces.
Features
s Low power consumption
s 20 MHz to 85 MHz shift clock support
s r1V common-mode range around 1.2V
s Narrow bus reduces cable size and cost
s High throughput (up to 2.38 Gbps throughput)
s Internal PLL with no external component
s Compatible with TIA/EIA-644 specification
s Devices are offered 56-lead TSSOP packages
Ordering Code:
Order Number Package Number
Package Description
FIN3383MTD
MTD56
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
FIN3384MTD
MTD56
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
FIN3385MTD
MTD56
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
FIN3386MTD
MTD56
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Part
FIN3385
FIN3383
FIN3386
FIN3384
TABLE 1. Display Panel Link Serializers/Deserializers Chip Matrix
CLK Frequency
85
66
85
66
LVTTL IN
28
28
LVDS OUT
4
4
LVDS IN LVTTL OUT
4 28
4 28
Package
56 TSSOP
56 TSSOP
56 TSSOP
56 TSSOP
© 2005 Fairchild Semiconductor Corporation DS500864
www.fairchildsemi.com






FIN3383 Datasheet, Funktion
Absolute Maximum Ratings(Note 7)
Power Supply Voltage (VCC)
TTL/CMOS Input/Output Voltage
-0.3V to +4.6V
0.5V to 4.6V
LVDS Input/Output Voltage
-0.3V to +4.6V
LVDS Output Short Circuit Current (IOSD)
Continuous
Storage Temperature Range (TSTG)
65qC to 150qC
Maximum Junction Temperature (TJ)
150qC
Lead Temperature (TL)
(Soldering, 4 seconds)
260qC
ESD Rating (HBM, 1.5 k:, 100 pF)
I/O to GND
!10.0 kV
All Pins
!6.5 kV
ESD Rating (MM, 0:, 200 pF)
!400V
Recommended Operating
Conditions
Supply Voltage (VCC)
Operating Temperature (TA)(Note 7)
Maximum Supply Noise Voltage
(VCCNPP)
3.0V to 3.6V
10°C to 70°C
100 mVP-P (Note 8)
Note 7: Absolute maximum ratings are DC values beyond which the device
may be damaged or have its useful life impaired. The datasheet specifica-
tions should be met, without exception, to ensure that the system design is
reliable over its power supply, temperature, and output/input loading vari-
ables. Fairchild does not recommend operation outside datasheet specifi-
cations.
Note 8: 100mV VCC noise should be tested for frequency at least up to
2 MHz. All the specification below should be met under such a noise.
Transmitter DC Electrical Characteristics
Over supply voltage and operating temperature ranges, unless otherwise specified. (Note 9)
Symbol
Parameter
Test Conditions
Transmitter LVTTL Input Characteristics
VIH Input High Voltage
VIL Input Low Voltage
VIK Input Clamp Voltage
IIN Input Current
Transmitter LVDS Output Characteristics (Note 10)
IIK 18 mA
VIN 0.4V to 4.6V
VIN GND
VOD
'VOD
VOS
'VOS
IOS
Output Differential Voltage
VOD Magnitude Change from Differential LOW-to-HIGH
Offset Voltage
RL 100 :, See Figure 1
Offset Magnitude Change from Differential LOW-to-HIGH
Short Circuit Output Current
VOUT 0V
IOZ Disabled Output Leakage Current
Transmitter Supply Current
DO 0V to 4.6V, PwrDn 0V
ICCWT
28:4 Transmitter Power Supply Current
for Worst Case Pattern (With Load)
(Note 11)
RL 100 :,
See Figure 3
32.5 MHz
40.0 MHz
66.0 MHz
85.0 MHz
Min
2.0
GND
10.0
250
1.125
Typ
0.79
1.8
0
TBD
1.25
3.5
r1.0
31.0
32.0
37.0
42.0
Max
VCC
0.8
1.5
10.0
450
35.0
1.375
5.0
r10.0
49.5
55.0
60.5
66.0
Units
V
V
V
PA
mV
mV
V
mV
mA
PA
mA
ICCPDT
ICCGT
Powered Down Supply Current
28:4 Transmitter Supply Current
for 16 Grayscale (Note 11)
PwrDn 0.8V
See Figure 21
(Note 12)
32.5 MHz
40.0 MHz
65.0 MHz
10.0
55.0
PA
29.0
41.8
30.0
35.0
44.0
49.5
mA
85.0 MHz
39.0
55.0
Note 9: All Typical values are at TA 25qC and with VCC 3.3V.
Note 10: Positive current values refer to the current flowing into device and negative values means current flowing out of pins. Voltage are referenced to
ground unless otherwise specified (except 'VOD and VOD).
Note 11: The power supply current for both transmitter and receiver can be different with the number of active I/O channels.
Note 12: The 16-grayscale test pattern tests device power consumption for a typicalLCD display pattern. The test pattern approximates signal switching
needed to produce groups of 16 vertical strips across the display.
www.fairchildsemi.com
6

6 Page









FIN3383 pdf, datenblatt
AC Loading and Waveforms (Continued)
FIGURE 7. Transmitter Outputs Channel-to-Channel Skew
Note: For the receiver with falling-edge strobe, the definition of setup/hold time will be slightly different from the one with rising-edge strobe. The clock refer-
ence point is the time when the clock falling edge passes through 2V. For hold time tRHRC, the clock reference point is the time when falling edge passes
through 0.8V.
FIGURE 8. (Receiver) Setup/Hold and HIGH/LOW Times
FIGURE 9. Transmitter Clock In to Clock Out Delay (Rising Edge Strobe)
FIGURE 10. Receiver Clock In to Clock Out Delay (Falling Edge Strobe)
www.fairchildsemi.com
12

12 Page





SeitenGesamt 18 Seiten
PDF Download[ FIN3383 Schematic.PDF ]

Link teilen




Besondere Datenblatt

TeilenummerBeschreibungHersteller
FIN3383(FIN3383 - FIN3386) Low Voltage 28-Bit Flat Panel Display Link Serializers/DeserializersFairchild Semiconductor
Fairchild Semiconductor
FIN3384(FIN3383 - FIN3386) Low Voltage 28-Bit Flat Panel Display Link Serializers/DeserializersFairchild Semiconductor
Fairchild Semiconductor
FIN3385(FIN3383 - FIN3386) Low Voltage 28-Bit Flat Panel Display Link Serializers/DeserializersFairchild Semiconductor
Fairchild Semiconductor
FIN3386(FIN3383 - FIN3386) Low Voltage 28-Bit Flat Panel Display Link Serializers/DeserializersFairchild Semiconductor
Fairchild Semiconductor

TeilenummerBeschreibungHersteller
CD40175BC

Hex D-Type Flip-Flop / Quad D-Type Flip-Flop.

Fairchild Semiconductor
Fairchild Semiconductor
KTD1146

EPITAXIAL PLANAR NPN TRANSISTOR.

KEC
KEC


www.Datenblatt-PDF.com       |      2020       |      Kontakt     |      Suche