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ZL40814 Schematic ( PDF Datasheet ) - Zarlink Semiconductor

Teilenummer ZL40814
Beschreibung (ZL40813 - ZL40818) 13.5GHz Fixed Modulus Dividers
Hersteller Zarlink Semiconductor
Logo Zarlink Semiconductor Logo 




Gesamt 15 Seiten
ZL40814 Datasheet, Funktion
www.DataSheet4U.com
Features
• Very High Operating Speed
• Low Phase Noise (Typically better than
-146dBc/Hz at 10kHz offset)
• 5V Single Supply Operation
• Low Power Dissipation: 500mW (Typ)
• Surface Mount Plastic Package with Exposed
Pad (See Application Notes)
Prescaler Modulus
• ZL40813 - Divide by 8
• ZL40814 - Divide by 16
• ZL40818 - Divide by 4
Applications
• 10.5 to 13.5GHz PLL applications
• LMDS
• Instrumentation
• Satellite Communications
• Fibre Optic Communications; OC48, OC192
• Ultra Low Jitter Clock Systems
ZL40813/14/18
13.5GHz Fixed Modulus Dividers
Data Sheet
July 2003
Ordering Information
ZL40813/DCE (tubes)
ZL40813/DCF (tape and reel)
ZL40814/DCE (tubes)
ZL40814/DCF (tape and reel)
ZL40818/DCE (tubes)
ZL40818/DCF (tape and reel)
8 pin SOIC
8 pin SOIC
8 pin SOIC
8 pin SOIC
8 pin SOIC
8 pin SOIC
-40°C to +85°C
Description
The ZL40813, 14 and 18 are 5V supply, very high
speed low power prescalers for professional
applications with a fixed modulus of 8, 16, or 4
respectively. The dividing elements are dynamic D type
flip flops and allow operation from 10.5GHz to 13.5GHz
with a sinewave input (Note these prescalers are not
suitable for D.C. operation). The output stage has
internal 50 ohm pull up giving a 1v p-p output. See
application notes for more details.
VCC IN
1
Vref
50 Ohm
Div N
VCC OUT
8
OUTPUT
OUTPUT B
7
6
INPUT
2
INPUT B
3
400 Ohm
GND
4
20mA
GND
5
Figure 1 - Functional Block Diagram
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2003, Zarlink Semiconductor Inc. All Rights Reserved.






ZL40814 Datasheet, Funktion
ZL40813/14/18
Data Sheet
20.00
10.00
0.00
-10.00
-20.00
ZL40814 Typical Input Sensitivity (Sinewave Drive) @ -40 to +85 DegC
85 DegC
70 DegC
25 DegC
Guaranteed Operating
W indow
25C
-40C
85C
Max
70C
-30.00
-40.00
8
9 10 11 12 13 14 15 16
Input Frequency (GHz)
Figure 5 - Graph of Input Sensitivity @ -40, +25, +70 and +85 Deg C.
Phase Noise vs Offset Freq in = 10GHz
Pin = -1dBm, 5.25V, Temp = 25C
-120
-125
-130
-135
-140
-145
-150
0.1
1 10
Offset Frequency in kHz
100
ZL40818
ZL40813
ZL40814
Figure 6 - 13.5GHz Prescalers; Phase Noise vs Offset Frequency
6
Zarlink Semiconductor Inc.

6 Page









ZL40814 pdf, datenblatt
ZL40813/14/18
Data Sheet
Figure 17 - Differential output waveform, showing reduced feedthrough of the input waveform
VCC = 5V, Vin = 2dBm, Fin = 10GHz.
5.0 Application Notes
5.1 Application Circuit
Figure 3 illustrates the recommended Single Ended Application Circuit. This represents the circuit used to complete
characterisation. The tabulated Electrical performance is guaranteed using this application circuit.
A blank application board is available.
5.1.1 Circuit Options
The application circuit includes some optional components that may be required to improve tolerance of system
noise present in the application.
Dummy R source may be added to the inverting input to provide a better matched source impedance at the input.
This will improve the rejection of common mode noise present within the system.
Dummy R load may be added to the inverting output to provide better matched load at the output. This will reduce
the radiated EMI at the output and reduce the Output Noise present on the supply rail.
Rfilter can be inserted between the Vcc in and the Vcc_out to provide additional filtering to the input Vcc. The input
Vcc powers the input bias reference only and can be a sensitive point to system noise. The nominal input current at
Vcc_IN s 0.35mA. An alternative would be to use an inductive choke.
C1 is additional Supply Filtering and should be added with Rfilter. The IC includes 10pF of on Chip Supply Filtering.
12
Zarlink Semiconductor Inc.

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