PDF ZL38010 Data sheet ( Hoja de datos )

Número de pieza	ZL38010
Descripción	Low Power Quad ADPCM Transcoder
Fabricantes	Zarlink Semiconductor
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No Preview Available ! www.DataSheet4U.com ZL38010 Low Power Quad ADPCM Transcoder Data Sheet Features • Full duplex transcoder with four encode channels and four decode channels • 32 kbps, 24 kbps and 16 kbps ADPCM coding complying with ITU-T (previously CCITT) G.726 (without 40 kbps), and ANSI T1.303-1989 • Low power operation, 6.5 mW typical • Asynchronous 4.096 MHz master clock operation • SSI and ST-BUS interface options • Transparent PCM bypass • Transparent ADPCM bypass • Linear PCM code • No microprocessor control required • Simple interface to Codec devices • Pin selectable µ−Law or A-Law operation • Pin selectable ITU-T or signed magnitude PCM coding • Single 3.3 Volts power supply January 2007 Ordering Information ZL38010DCE 28 Pin SOIC ZL38010DCF 28 Pin SOIC ZL38010DCE1 28 Pin SOIC ZL38010DCF1 28 Pin SOIC **Pb Free Matte Tin -40°C to +85°C Tubes Tape & Reel Tubes Tape & Reel Applications • Pair gain • Voice mail systems • Wireless telephony systems Description The Quad ADPCM Transcoder is a low power, CMOS device capable of four encode and four decode functions per frame. Four 64 kbps PCM octets are compressed into four 32, 24 or 16 kbps ADPCM words, and four 32, 24 or 16 kbps ADPCM words are expanded into four 64 kbps PCM octets. The 32, 24 and 16 kbps ADPCM transcoding algorithms utilized conform to ITU-T Recommendation G.726 (excluding 40 kbps), and ANSI T1.303 - 1989. ADPCMi ADPCMo ENB1 ENB2/F0od BCLK F0i MCLK C2o EN1 EN2 ADPCM I/O Full Duplex Quad Transcoder PCM I/O PCMo1 PCMi1 PCMo2 PCMi2 Timing Control Decode VDD VSS PWRDN IC MS1 MS2 MS3 A/µ FORMAT MS4 MS5 MS6 LINEAR SEL Figure 1 - Functional Block Diagram 1 Zarlink Semiconductor Inc. Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2005-2007, Zarlink Semiconductor Inc. All Rights Reserved. 1 page ZL38010 Data Sheet Functional Description The Quad-channel ADPCM Transcoder is a low power, CMOS device capable of four encode and four decode operations per frame. Four 64 kbps channels (PCM octets) are compressed into four 32, 24 or 16 kbps ADPCM channels (ADPCM words), and four 32, 24 or 16 kbps ADPCM channels (ADPCM words) are expanded into four 64 kbps PCM channels (PCM octets). The ADPCM transcoding algorithm utilized conforms to ITU-T recommendation G.726 (excluding 40 kbps), and ANSI T1.303 - 1989. Switching on-the-fly between 32 and 24 kbps transcoding is possible by toggling the appropriate mode select pins (supports T1 robbed-bit signalling). All functions supported by the device are pin selectable. The four encode functions comprise a common group controlled via Mode Select pins MS1, MS2 and MS3. Similarly, the four decode functions form a second group commonly controlled via Mode Select pins MS4, MS5 and MS6. All other pin controls are common to the entire transcoder. The device requires 6.5 mWatts (MCLK= 4.096 MHz) typically for four channel transcode operation. A minimum master clock frequency of 4.096 MHz is required for the circuit to complete four encode channels and four decode channels per frame. For SSI operation a master clock frequency greater than 4.096 MHz and asynchronous, relative to the 8 kHz frame, is allowed. The PCM and ADPCM serial busses support both ST-BUS and Synchronous Serial Interface (SSI) operation. This allows serial data clock rates from 128 kHz to 4096 kHz, as well as compatibility with Zarlink’s standard Serial Telecom BUS (ST-BUS). For ST-BUS operation, on chip channel counters provide channel enable outputs as well as a 2048 kHz bit clock output which may be used by down-stream devices utilizing the SSI bus interface. Linear coded PCM is also supported. In this mode the encoders compress, four 14-bit, two’s complement (S,S,S,12,...,1,0), uniform PCM channels into four 4, 3 or 2 bit ADPCM channels. Similarly, the decoder expands four 4, 3 or 2 bit ADPCM channels into four 16-bit, two’s complement (S,14,...,1,0), uniform PCM channels. The data rate for both ST-BUS and SSI operation in this mode is 2048 kbps. 5 Zarlink Semiconductor Inc. 5 Page ZL38010 Data Sheet Bit Clock (BCLK) For SSI operation the bit rate, for both ADPCM and PCM ports, is determined by the clock input at BCLK. BCLK must be eight periods in duration and synchronous with the 8 kHz frame inputs at ENB1 and ENB2. Data is sampled at PCMi1/2 and at ADPCMi concurrent with the falling edge of BCLK. Data is available at PCMo1/2 and ADPCMo concurrent with the rising edge of BCLK. BCLK may be any rate between 128 kHz and 4096 kHz. For ST- BUS operation BCLK is ignored (tie to VSS) and the bit rate is internally set to 2048 kbps. BCLK ENB1 ENB2/F0od PCMi/o1 PCMi/o2 ADPCM i/o 32 kbps 24 kbps B1 B2 7654321076543210 B3 B4 7654321076543210 12 341 23 4 1 23 41 23 4 B1 B2 B3 B4 123x123x 123x123x ADPCM i/o B1 B2 B3 B4 B1 B2 B3 B4 16 kbps X = undetermined logic level output; don’t care input Outputs high impedance outside of channel strobe boundaries Two frame delay from data input to data output 1 21 2 1 2 1 21 2 1 2 1 2 1 2 SEL = 0 SEL = 1 SEL for 16 kbps only Figure 4 - SSI 8-Bit Companded PCM Relative Timing 11 Zarlink Semiconductor Inc. 11 Page

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