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STE100A Schematic ( PDF Datasheet ) - ST Microelectronics

Teilenummer STE100A
Beschreibung PCI 10/100 Ethernet controller
Hersteller ST Microelectronics
Logo ST Microelectronics Logo 




Gesamt 30 Seiten
STE100A Datasheet, Funktion
www.DataSheet4U.com
STE10/100A
PCI 10/100 Ethernet controller with integrated PHY (3.3V)
Features
IEEE802.3u 100BASE-TX and IEEE802.3
10BASE-T compliant
Support for IEEE802.3x flow control
IEEE802.3u auto-negotiation support for
10BASE-T and 100BASE-TX
PCI bus interface rev. 2.2 compliant
ACPI and PCI power management standard
compliant
Support for PC99 wake on LAN
Provides 32-bit PCI bus master data transfer at
PCI clocks of 20-33 MHz
Provides writable EEPROM/Boot rom interface
Provides independent transmission and
receiving FIFOs, each 2k bytes long
Supports big endian or little endian byte
ordering
ACPI and PCI compliant power management
functions offer significant power-savings
performance
Provides general purpose timers
128-pin QFP package
PQFP128 (14mm x 20mm x 2.7mm)
Description
The STE10/100A is a high performing PCI fast
ethernet controller with integrated physical layer
interface for 10BASE-T and 100BASE-TX
applications.
It was designed with advanced CMOS technology
to provide glueless 32-bit bus master interface for
PCI bus, boot ROM interface, CSMA/CD protocol
for fast ethernet, as well as the physical media
interface for 100BASE-TX of IEEE802.3u and
10BASE-T of IEEE802.3. The auto-negotiation
function is also supported for speed and duplex
detection.
The STE10/100A provides both half-duplex and
full-duplex operation, as well as support for full-
duplex flow control. It provides long FIFO buffers
for transmission and receiving, and early interrupt
mechanism to enhance performance. The
STE10/100A also supports ACPI and PCI
compliant power management function
February 2007
Rev 8
1/82
www.st.com
82






STE100A Datasheet, Funktion
Overview
STE10/100A
LED display
Provides 2 LED display modes:
– 3 LED displays for
100Mbps (on) or 10Mbps (off) link (remains on when link ok) or activity (Blinks at
10Hz when receiving or transmitting collision-free) FD (Remains on when in full
duplex mode) or when collision detected (Blinks at 20Hz)
– 4 LED displays for:
100 link (On when 100M link ok)
10 link (On when 10M link ok)
Activity (Blinks at 10Hz when receiving or transmitting)
FD (Remains on when in full duplex mode) or when collision detected (Blinks at
20Hz)
If no LED is used, then: Pull the pins 90, 91, 92 of U4 to high with 4.7K resistor (see
STE10/100A evaluation board schematics for details)
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6 Page









STE100A pdf, datenblatt
Functional description
3 Functional description
3.1 Initialization flow
Figure 4. STE10/100A initialization flow
Search NIC
STE10/100A
Get base IO address
Get IRQ value
Reset MAC (CSR0)
Reset PHY (XR0)
Need set
Yes
No
Read EEPROM from CSR9
Set physical address (CSR25, 26)
(Force media)
Program the media type to XR0
Need set
No
A
Yes
Set multimedia address table
(CSR27, 28)
Prepare transmit descriptor and buffer
Prepare receive descriptor and buffer
Install NIC ISR function
Open NIC interrupt
Enable Tx & Rx functions
END
PC00349
12/82

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