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ZL30123 Schematic ( PDF Datasheet ) - Zarlink Semiconductor

Teilenummer ZL30123
Beschreibung Low Jitter Line Card Synchronizer
Hersteller Zarlink Semiconductor
Logo Zarlink Semiconductor Logo 




Gesamt 27 Seiten
ZL30123 Datasheet, Funktion
www.DataSheet4U.com
ZL30123
SONET/SDH
Low Jitter Line Card Synchronizer
Data Sheet
A full Design Manual is available to qualified customers.
To register, please send an email to
Features
• Synchronizes with standard telecom system
references and synthesizes a wide variety of
protected telecom line interface clocks that are
compliant with Telcordia GR-253-CORE and ITU-T
G.813
• Internal APLL provides standard output clock
frequencies up to 622.08 MHz with jitter < 3 ps
RMS suitable for GR-253-CORE OC-12 and G.813
STM-16 interfaces
• Programmable output synthesizers (P0, P1)
generate clock frequencies from any multiple of
8 kHz up to 77.76 MHz in addition to 2 kHz
• Provides two DPLLs which are independently
configurable through a serial peripheral interface
• DPLL1 provides all the features necessary for
generating SONET/SDH compliant clocks including
automatic hitless reference switching, automatic
mode selection (locked, free-run, holdover), and
selectable loop bandwidth
Ordering Information
May 2006
ZL30123GGG 100 Pin CABGA Trays
ZL30123GGG2 100 Pin CABGA* Trays
*Pb Free Tin/Silver/Copper
-40oC to +85oC
• DPLL2 provides a comprehensive set of features
for generating derived output clocks and other
general purpose clocks
• Provides 8 reference inputs which support clock
frequencies with any multiples of 8 kHz up to
77.76 MHz in addition to 2 kHz
• Provides 3 sync inputs for output frame pulse
alignment
• Generates several styles of output frame pulses
with selectable pulse width, polarity, and frequency
• Configurable input to output delay, and output to
output phase alignment
• Flexible input reference monitoring automatically
disqualifies references based on frequency and
phase irregularities
• Supports IEEE 1149.1 JTAG Boundary Scan
osco
osci
ref0
ref1
ref2
ref3
ref4
ref5
ref6
ref7
sync0
sync1
sync2
int_b
trst_b tck tdi tms tdo dpll2_ref
dpll1_hs_en dpll1_lock dpll1_holdover diff0_en diff1_en
Master
Clock
IEEE 1449.1
JTAG
ref7:0
sync2:0
Reference ref_&_sync_status
Monitors
DPLL2
ref
ref
DPLL1
sync
fb_clk/fp
P0
Synthesizer
P1
Synthesizer
SONET/SDH
APLL
Feedback
Synthesizer
p0_clk0
p0_clk1
p0_fp0
p0_fp1
p1_clk0
p1_clk1
diff0
diff1
sdh_clk0
sdh_clk1
sdh_fp0
sdh_fp1
fb_clk
SPI Interface
Controller &
State Machine
sck si so cs_b
rst_b
dpll1_mod_sel1:0
sdh_filter filter_ref0 filter_ref1
Figure 1 - Block Diagram
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2006, Zarlink Semiconductor Inc. All Rights Reserved.






ZL30123 Datasheet, Funktion
ZL30123
Data Sheet
Pin Description
Pin #
Name
I/O
Type
Description
Input Reference
C1 ref0
B2 ref1
A3 ref2
C3 ref3
B3 ref4
B4 ref5
C4 ref6
A4 ref7
Id Input References (LVCMOS, Schmitt Trigger). These are input references
available to both DPLL1 and DPLL2 for synchronizing output clocks. All eight
input references can be automatically or manually selected using software
registers. These pins are internally pulled down to Vss.
B1 sync0
A1 sync1
A2 sync2
Id Frame Pulse Synchronization References (LVCMOS, Schmitt Trigger).
These are the frame pulse synchronization inputs associated with input
references 0, 1 and 2. These inputs accept frame pulses in a clock format (50%
duty cycle) or a basic frame pulse format with minimum pulse width of 5 ns.
These pins are internally pulled down to Vss.
Output Clocks and Frame Pulses
D10 sdh_clk0
O SONET/SDH Output Clock 0 (LVCMOS). This output can be configured to
provide any one of the SONET/SDH clock outputs up to 77.76 MHz. The default
frequency for this output is 77.76 MHz.
G10 sdh_clk1
O SONET/SDH Output Clock 1 (LVCMOS). This output can be configured to
provide any one of the SONET/SDH clock outputs up to 77.76 MHz. The default
frequency for this output is 19.44 MHz.
E10 sdh_fp0
O SONET/SDH Output Frame Pulse 0 (LVCMOS). This output can be configured
to provide virtually any style of output frame pulse synchronized with an
associated SONET/SDH family output clock. The default frequency for this frame
pulse output is 8 kHz.
F10 sdh_fp1
K9 p0_clk0
K7 p0_clk1
O SONET/SDH Output Frame Pulse 1 (LVCMOS). This output can be configured
to provide virtually any style of output frame pulse synchronized with an
associated SONET/SDH family output clock. The default frequency for this frame
pulse output is 2 kHz.
O Programmable Synthesizer 0 - Output Clock 0 (LVCMOS). This output can be
configured to provide any frequency with a multiple of 8 kHz up to 77.76 MHz in
addition to 2 kHz. The default frequency for this output is 2.048 MHz.
O Programmable Synthesizer 0 - Output Clock 1 (LVCMOS). This is a
programmable clock output configurable as a multiple or division of the p0_clk0
frequency within the range of 2 kHz to 77.76 MHz. The default frequency for this
output is 8.192 MHz.
K8 p0_fp0
J7 p0_fp1
O Programmable Synthesizer 0 - Output Frame Pulse 0 (LVCMOS). This output
can be configured to provide virtually any style of output frame pulse associated
with the p0 clocks. The default frequency for this frame pulse output is 8 kHz.
O Programmable Synthesizer 0 - Output Frame Pulse 1 (LVCMOS). This output
can be configured to provide virtually any style of output frame pulse associated
with the p0 clocks. The default frequency for this frame pulse output is 8 kHz.
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6 Page









ZL30123 pdf, datenblatt
ZL30123
Data Sheet
1.2 DPLL Mode Control
Both DPLL1 and DPLL2 independently support three modes of operation - free-run, normal and holdover. The
mode of operation can be manually set or controlled by an automatic state machine as shown in Figure 2.
Reset
Free-Run
All references are monitored
for frequency accuracy and
phase regularity, and at least
one reference is qualified.
Another reference is
qualified and available
for selection
No references are
qualified and
available for
selection
Holdover
Lock
Acquisition
Phase lock on
the selected
reference is
achieved
Selected reference
fails
NNoorrmmaall
((LLockeedd))
Figure 2 - Automatic Mode State Machine
Free-run
The free-run mode occurs immediately after a reset cycle or when the DPLL has never been synchronized to a
reference input. In this mode, the frequency accuracy of the output clocks is equal to the frequency accuracy of the
external master oscillator.
Lock Acquisition
The input references are continuously monitored for frequency accuracy and phase regularity. If at least one of the
input references is qualified by the reference monitors, then the DPLL will begin lock acquisition on that input. Given
a stable reference input, the ZL30123 will enter in the Normal (locked) mode.
Normal (locked)
The usual mode of operation for the DPLL is the normal mode where the DPLL phase locks to a selected qualified
reference input and generates output clocks and frame pulses with a frequency accuracy equal to the frequency
accuracy of the reference input. While in the normal mode, the DPLL’s clock and frame pulse outputs comply with
the MTIE and TDEV wander generation specifications as described in Telcordia and ITU-T telecommunication
standards.
Holdover
When the DPLL operating in the normal mode loses its reference input, and no other qualified references are
available, it will enter the holdover mode and continue to generate output clocks based on historical frequency data
collected while the DPLL was synchronized.
12
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