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ZL30111 Schematic ( PDF Datasheet ) - Zarlink Semiconductor

Teilenummer ZL30111
Beschreibung POTS Line Card PLL
Hersteller Zarlink Semiconductor
Logo Zarlink Semiconductor Logo 




Gesamt 20 Seiten
ZL30111 Datasheet, Funktion
www.DataSheet4U.com
ZL30111
POTS Line Card PLL
Data Sheet
Features
January 2007
• Synchronizes to 8 kHz, 2.048 MHz, 8.192 MHz or
19.44 MHz input
• Provides a range of clock outputs: 2.048 MHz,
4.096 MHz and 8.192 MHz
• Provides 2 styles of 8 kHz framing pulses
• Automatic entry and exit from freerun mode on
reference fail
Ordering Information
ZL30111QDG
ZL30111QDG1
64 Pin TQFP Trays, Bake & Drypack
64 Pin TQFP* Trays, Bake & Drypack
*Pb Free Matte Tin
-40°C to +85°C
Applications
• Provides DPLL lock and reference fail indication
• Synchronizer for POTS line cards
• DPLL bandwidth of 922 Hz for all rates of input
reference and 58 Hz for an 8 kHz input reference
• Rate convert NTR 8kHz or GPON physical
interface clock to TDM clock
• Less than 0.6 nspp intrinsic jitter on all output clocks Description
• 20 MHz external master clock source: clock
oscillator or crystal
The ZL30111 POTS line card PLL contains a digital
• Simple hardware control interface
phase-locked loop (DPLL), which provides timing and
synchronization for SLIC/CODEC devices.
The ZL30111 generates TDM clock and framing
signals that are phase locked to the input reference.
It helps ensure system reliability by monitoring its
reference for stability and by maintaining stable
output clocks during short periods when the
reference is unavailable.
REF
RST
OSCi
OSCo
REF_FAIL
LOCK
Reference
Monitor
State Machine
Master
Clock
Mode
Control
DPLL
C2o
C4
C8
F4
F8
Figure 1 - Functional Block Diagram
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2007, Zarlink Semiconductor Inc. All Rights Reserved.






ZL30111 Datasheet, Funktion
ZL30111
Data Sheet
Pin Description (continued)
Pin #
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
Name
IC
IC
AVDD
NC
NC
IC
AGND
AGND
AVCORE
AVDD
AVDD
NC
NC
AGND
AGND
C4
C8
AVDD
AVDD
C2o
Description
Internal Connection. Connect this pin to GND.
Internal Connection. Connect this pin to GND.
Positive Analog Supply Voltage. +3.3 VDC nominal.
No internal bonding Connection. Leave unconnected.
No internal bonding Connection. Leave unconnected.
Internal Connection. Leave unconnected.
Analog Ground. 0 V
Analog Ground. 0 V
Positive Analog Supply Voltage. +1.8 VDC nominal.
Positive Analog Supply Voltage. +3.3 VDC nominal.
Positive Analog Supply Voltage. +3.3 VDC nominal.
No internal bonding Connection. Leave unconnected.
No internal bonding Connection. Leave unconnected.
Analog Ground. 0 V
Analog Ground. 0 V
Clock 4.096 MHz (Output). This output is used for ST-BUS operation at 2.048 Mbps or
4.096 Mbps.
Clock 8.192 MHz (Output). This output is used for ST-BUS and GCI operation at
8.192 Mbps.
Positive Analog Supply Voltage. +3.3 VDC nominal.
Positive Analog Supply Voltage. +3.3 VDC nominal.
Clock 2.048 MHz (Output). This output is used for standard E1 interface timing.
This clock output pad includes a Schmitt input which serves as a PLL feedback path;
proper transmission-line termination should be applied to maintain reflections below
Schmitt trigger levels.
47 IC Internal Connection. Leave unconnected.
48 F8 Frame Pulse (Output). This is an 8 kHz 122 ns active high framing pulse, which marks
the beginning of a frame.
This clock output pad includes a Schmitt input which serves as a PLL feedback path;
proper transmission-line termination should be applied to maintain reflections below
Schmitt trigger levels.
49 F4 Frame Pulse ST-BUS 2.048 Mbps (Output). This output is an 8 kHz 244 ns active low
framing pulse, which marks the beginning of an ST-BUS frame. This is typically used for
ST-BUS operation at 2.048 Mbps and 4.096 Mbps.
50 IC Internal Connection. Leave unconnected.
51
AGND
Analog Ground. 0 V
6
Zarlink Semiconductor Inc.

6 Page









ZL30111 pdf, datenblatt
ZL30111
Data Sheet
5.0 Applications
This section contains ZL30111 application specific details for power supply decoupling, reset operation, clock and
crystal operation.
5.1 Power Supply Decoupling
Jitter levels on the ZL30111 output clocks may increase if the device is exposed to excessive noise on its power
pins. For optimal jitter performance, the ZL30111 device should be isolated from noise on power planes connected
to its 3.3 V and 1.8 V supply pins. For recommended common layout practices, refer to Zarlink Application Note
ZLAN-178.
5.2 Master Clock
The ZL30111 can use either a clock or crystal as the master timing source.
5.2.1 Clock Oscillator
When selecting a clock oscillator, numerous parameters must be considered. This includes absolute frequency,
frequency change over temperature, output rise and fall times, output levels, duty cycle and phase noise.
The output clock should be connected directly (not AC coupled) to the OSCi input of the ZL30111, and the OSCo
output should be left open as shown in Figure 5.
1 Frequency
2 Tolerance
3 Rise & fall time
4 Duty cycle
20 MHz
as required (better than +/-50ppm)
< 8 ns
40% to 60%
Table 1 - Clock Oscillator Specification
ZL30111
OSCi
+3.3 V
+3.3 V
20 MHz OUT
GND
0.1 µF
OSCo
No Connection
Figure 5 - Clock Oscillator Circuit
12
Zarlink Semiconductor Inc.

12 Page





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