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PDF SST34HF162G Data sheet ( Hoja de datos )
| Número de pieza | SST34HF162G | |
| Descripción | (SST34HF162G / SST34HF164G) 16 Mbit Dual-Bank Flash + 2/4 Mbit SRAM ComboMemory | |
| Fabricantes | SST | |
| Logotipo |  |
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16 Mbit Dual-Bank Flash + 2/4 Mbit SRAM ComboMemory
SST34HF162G / SST34HF164G
SST34HF162G/164G16Mb Dual-Bank Flash + 2/4 Mb SRAM MCP ComboMemory
FEATURES:
Preliminary Specifications
• Flash Organization: 1M x16
– 16 Mbit: 12 Mbit + 4 Mbit
• Concurrent Operation
– Read from or Write to SRAM while
Erase/Program Flash
• SRAM Organization:
– 2 Mbit:128K x16
– 4 Mbit: 256K x16
• Single 2.7-3.3V Read and Write Operations
• Superior Reliability
– Endurance: 100,000 Cycles (typical)
– Greater than 100 years Data Retention
• Low Power Consumption: (typical values @ 5 MHz)
– Active Current: Flash 10 mA (typical)
SRAM 6 mA (typical)
– Standby Current: 10 µA (typical)
• Hardware Sector Protection (WP#)
– Protects 4 outer most sectors (4 KWord) in the
larger bank by holding WP# low and unprotects
by holding WP# high
• Hardware Reset Pin (RST#)
– Resets the internal state machine to reading
data array
• Sector-Erase Capability
– Uniform 2 KWord sectors
• Block-Erase Capability
– Uniform 32 KWord blocks
• Read Access Time
– Flash: 70 ns
– SRAM: 70 ns
• Erase-Suspend / Erase-Resume Capabilities
• Latched Address and Data
• Fast Erase and Word-Program (typical):
– Sector-Erase Time: 18 ms
– Block-Erase Time: 18 ms
– Chip-Erase Time: 35 ms
– Program Time: 7 µs
• Automatic Write Timing
– Internal VPP Generation
• End-of-Write Detection
– Toggle Bit
– Data# Polling
• CMOS I/O Compatibility
• JEDEC Standard Command Set
• Packages Available
– 48-ball LFBGA (6mm x 8mm)
– 48-ball LBGA (10mm x 12mm)
– Non-Pb (lead-free) packages available
PRODUCT DESCRIPTION
The SST34HF16xG ComboMemory devices integrate a
1M x16 CMOS flash memory bank with either 128K x16 or
256K x16 CMOS SRAM memory bank in a multi-chip
package (MCP). These devices are fabricated using SST’s
proprietary, high-performance CMOS SuperFlash technol-
ogy incorporating the split-gate cell design and thick-oxide
tunneling injector to attain better reliability and manufactur-
ability compared with alternate approaches. The
SST34HF16xG devices are ideal for applications such as
cellular phones, GPS devices, PDAs, and other portable
electronic devices in a low power and small form factor sys-
tem.
The SuperFlash technology provides fixed Erase and Pro-
gram times, independent of the number of Erase/Program
cycles that have occurred. Therefore, the system software
or hardware does not have to be modified or de-rated as is
necessary with alternative flash technologies, whose Erase
and Program times increase with accumulated Erase/Pro-
gram cycles. The SST34HF16xG devices offer a guaran-
teed endurance of 10,000 cycles. Data retention is rated at
greater than 100 years. With high-performance Program
©2004 Silicon Storage Technology, Inc.
S71276-00-000
11/04
1
operations, the flash memory banks provide a typical Pro-
gram time of 7 µsec. The entire flash memory bank can be
erased and programmed word-by-word in 4 seconds (typi-
cally) for the SST34HF16xG, when using interface features
such as Toggle Bit or Data# Polling to indicate the comple-
tion of Program operation. To protect against inadvertent
flash write, the SST34HF16xG devices contain on-chip
hardware and software data protection schemes.
The flash and SRAM operate as two independent memory
banks with respective bank enable signals. The memory
bank selection is done by two bank enable signals. The
SRAM bank enable signal, BES#, selects the SRAM bank.
The flash memory bank enable signal, BEF#, has to be
used with Software Data Protection (SDP) command
sequence when controlling the Erase and Program opera-
tions in the flash memory bank. The memory banks are
superimposed in the same memory address space where
they share common address lines, data lines, WE# and
OE# which minimize power consumption and area. See
Figure 1 for memory organization.
The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc.
ComboMemory is a trademark of Silicon Storage Technology, Inc.
These specifications are subject to change without notice.
1 page  
16 Mbit Dual-Bank Flash + 2/4 Mbit SRAM ComboMemory
SST34HF162G / SST34HF164G
Preliminary Specifications
Product Identification
The Product Identification mode identifies the device as
SST34HF162G or SST34HF164G and the manufacturer
as SST. This mode may be accessed by software opera-
tions only. The hardware device ID Read operation, which
is typically used by programmers cannot be used on this
device because of the shared lines between flash and
SRAM in the multi-chip package. Therefore, application of
high voltage to pin A9 may damage this device. Users may
use the software Product Identification operation to identify
the part (i.e., using the device ID) when using multiple man-
ufacturers in the same socket. For details, see Tables 4 and
5 for software operation, Figure 15 for the Software ID
Entry and Read timing diagram and Figure 23 for the ID
Entry command sequence flowchart.
TABLE 2: PRODUCT IDENTIFICATION
Manufacturer’s ID
Device ID
SST34HF16xG
ADDRESS
BK0000H
BK0001H
DATA
00BFH
734BH
T2.0 1276
Note: BK = Bank Address (A19-A18)
Product Identification Mode Exit
In order to return to the standard Read mode, the Software
Product Identification mode must be exited. Exit is accom-
plished by issuing the Software ID Exit command
sequence, which returns the device to the Read mode.
This command may also be used to reset the device to the
Read mode after any inadvertent transient condition that
apparently causes the device to behave abnormally, e.g.,
not read correctly. Please note that the Software ID Exit
command is ignored during an internal Program or Erase
operation. See Table 5 for software command codes, Fig-
ure 16 for timing waveform and Figure 23 for a flowchart.
SRAM Operation
With BES# low and BEF# high, the SST34HF162G/164G
operate as either 128K x16 or 256K x16 CMOS SRAM,
with fully static operation requiring no external clocks or
timing strobes. The SST34HF162G/164G SRAM is
mapped into the first 128 KWord address space. When
BES# and BEF# are high, all memory banks are dese-
lected and the device enters standby. Read and Write
cycle times are equal. The control signals UBS# and LBS#
provide access to the upper data byte and lower data byte.
See Table 4 for SRAM Read and Write data byte control
modes of operation.
SRAM Read
The SRAM Read operation of the SST34HF162G/164G is
controlled by OE# and BES#, both have to be low with
WE# high for the system to obtain data from the outputs.
BES# is used for SRAM bank selection. OE# is the output
control and is used to gate data from the output pins. The
data bus is in high impedance state when OE# is high.
Refer to the Read cycle timing diagram, Figure 4, for fur-
ther details.
SRAM Write
The SRAM Write operation of the SST34HF162G/164G is
controlled by WE# and BES#, both have to be low for the
system to write to the SRAM. During the Word-Write oper-
ation, the addresses and data are referenced to the rising
edge of either BES# or WE# whichever occurs first. The
write time is measured from the last falling edge of BES#
or WE# to the first rising edge of BES# or WE#. Refer to
the Write cycle timing diagrams, Figures 5 and 6, for fur-
ther details.
©2004 Silicon Storage Technology, Inc.
5
S71276-00-000
11/04
5 Page 
16 Mbit Dual-Bank Flash + 2/4 Mbit SRAM ComboMemory
SST34HF162G / SST34HF164G
Preliminary Specifications
TABLE 5: SOFTWARE COMMAND SEQUENCE
Command
Sequence
Program
Sector-Erase
Block-Erase
Chip-Erase
Erase-Suspend
Erase-Resume
Software ID Entry5
Software ID Exit
Software ID Exit
1st Bus
Write Cycle
Addr1 Data2
555H AAH
555H AAH
555H AAH
555H AAH
XXXXH B0H
XXXXH 30H
555H AAH
555H
XXH
AAH
F0H
2nd Bus
Write Cycle
Addr1 Data2
2AAH 55H
2AAH 55H
2AAH 55H
2AAH 55H
2AAH 55H
2AAH 55H
3rd Bus
Write Cycle
Addr1 Data2
555H A0H
555H 80H
555H 80H
555H 80H
BKX6
555H
555H
90H
F0H
4th Bus
Write Cycle
Addr1 Data2
WA3 Data
555H AAH
555H AAH
555H AAH
5th Bus
Write Cycle
Addr1 Data2
2AAH
2AAH
2AAH
55H
55H
55H
1. Address format A10-A0 (Hex), Addresses A19-A11 can be VIL or VIH, but no other value, for the command sequence.
2. DQ15-DQ8 can be VIL or VIH, but no other value, for the command sequence
3. WA = Program word address
4. SAX for Sector-Erase; uses A19-A10 address lines
BAX for Block-Erase; uses A19-A15 address lines
5. The device does not remain in Software Product Identification mode if powered down.
6. A19 and A18 = VIL
6th Bus
Write Cycle
Addr1 Data2
SAX4
BAX4
555H
30H
50H
10H
T5.0 1276
Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maximum
Stress Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation
of the device at these conditions or conditions greater than those defined in the operational sections of this data
sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.)
Operating Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -20°C to +85°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +125°C
D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5V to VDD1+0.3V
Transient Voltage (<20 ns) on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1.0V to VDD1+1.0V
Package Power Dissipation Capability (Ta = 25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W
Surface Mount Solder Reflow Temperature: . . . . . . . . . . . . . . . . . . . . . . . . . “with-Pb” units2: 240°C for 3 seconds
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . “non-Pb” units: 260°C for 3 seconds
Output Short Circuit Current3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
1. VDD = VDDF and VDDS
2. Certain “with-Pb” package types are capable of 260°C for 3 seconds; please consult the factory for the latest information.
3. Outputs shorted for no more than one second. No more than one output shorted at a time.
OPERATING RANGE
Range
Commercial
Extended
Ambient Temp
0°C to +70°C
-20°C to +85°C
VDD
2.7-3.3V
2.7-3.3V
AC CONDITIONS OF TEST
Input Rise/Fall Time . . . . . . . . . . . . . . 5 ns
Output Load . . . . . . . . . . . . . . . . . . . . CL = 30 pF
See Figures 19 and 20
©2004 Silicon Storage Technology, Inc.
11
S71276-00-000
11/04
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet SST34HF162G.PDF ] | |
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