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PDF SST32HF1641 Data sheet ( Hoja de datos )
| Número de pieza | SST32HF1641 | |
| Descripción | (SST32HFxxx1) Multi-Purpose Flash Plus + SRAM ComboMemory | |
| Fabricantes | SST | |
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Multi-Purpose Flash Plus + SRAM ComboMemory
SST32HF1641 / SST32HF1681 / SST32HF3241 / SST32HF3281
SST32HF1621C / SST32HF1641C / SST32HF3241C
FEATURES:
SST32HF324 / 32832Mb Flash + 4Mb SRAM, 32Mb Flash + 8Mb SRAM
(x16) MCP ComboMemories
Preliminary Specifications
• ComboMemories organized as:
– SST32HF1621C: 1M x16 Flash + 128K x16 SRAM
– SST32HF1641x: 1M x16 Flash + 256K x16 SRAM
– SST32HF1681: 1M x16 Flash + 256K x16 SRAM
– SST32HF3241x: 2M x16 Flash + 256K x16 SRAM
– SST32HF3281: 2M x16 Flash + 512K x16 SRAM
• Single 2.7-3.3V Read and Write Operations
• Concurrent Operation
– Read from or Write to SRAM while
Erase/Program Flash
• Superior Reliability
– Endurance: 100,000 Cycles (typical)
– Greater than 100 years Data Retention
• Low Power Consumption:
– Active Current: 15 mA (typical) for
Flash or SRAM Read
– Standby Current:
- SST32HFx1: 60 µA (typical)
- SST32HFx1C: 12 µA (typical)
• Flexible Erase Capability
– Uniform 2 KWord sectors
– Uniform 32 KWord size blocks
• Erase-Suspend/Erase-Resume Capabilities
• Security-ID Feature
– SST: 128 bits; User: 128 bits
• Hardware Block-Protection/WP# Input Pin
– Bottom Block-Protection (bottom 32 KWord)
• Fast Read Access Times:
– Flash: 70 ns
– SRAM: 70 ns
• Latched Address and Data for Flash
• Flash Fast Erase and Word-Program:
– Sector-Erase Time: 18 ms (typical)
– Block-Erase Time: 18 ms (typical)
– Chip-Erase Time: 40 ms (typical)
– Word-Program Time: 7 µs (typical)
• Flash Automatic Erase and Program Timing
– Internal VPP Generation
• Flash End-of-Write Detection
– Toggle Bit
– Data# Polling
• CMOS I/O Compatibility
• JEDEC Standard Command Set
• Package Available
– 63-ball LFBGA (8mm x 10mm x 1.4mm)
– 62-ball LFBGA (8mm x 10mm x 1.4mm)
• All non-Pb (lead-free) devices are RoHS compliant
PRODUCT DESCRIPTION
The SST32HFx1/x1C ComboMemory devices integrate
a CMOS flash memory bank with a CMOS SRAM mem-
ory bank in a Multi-Chip Package (MCP), manufactured
with SST’s proprietary, high performance SuperFlash
technology. The SST32HF16x1/32x1 devices use a
PseudoSRAM. The SST32HF16x1C/32x1C devices use
standard SRAM.
Featuring high performance Word-Program, the flash
memory bank provides a maximum Word-Program time of
7 µsec. To protect against inadvertent flash write, the
SST32HFx1/x1C devices contain on-chip hardware and
software data protection schemes. The SST32HFx1/x1C
devices offer a guaranteed endurance of 10,000 cycles.
Data retention is rated at greater than 100 years.
The SST32HFx1/x1C devices consist of two independent
memory banks with respective bank enable signals. The
Flash and SRAM memory banks are superimposed in the
same memory address space. Both memory banks share
common address lines, data lines, WE# and OE#. The
memory bank selection is done by memory bank enable
signals. The SRAM bank enable signal, BES# selects the
SRAM bank. The flash memory bank enable signal, BEF#
selects the flash memory bank. The WE# signal has to be
used with Software Data Protection (SDP) command
sequence when controlling the Erase and Program opera-
tions in the flash memory bank. The SDP command
sequence protects the data stored in the flash memory
bank from accidental alteration.
The SST32HFx1/x1C provide the added functionality of
being able to simultaneously read from or write to the
SRAM bank while erasing or programming in the flash
memory bank. The SRAM memory bank can be read or
written while the flash memory bank performs Sector-
Erase, Bank-Erase, or Word-Program concurrently. All
flash memory Erase and Program operations will automati-
cally latch the input address and data signals and complete
the operation in background without further input stimulus
requirement. Once the internally controlled Erase or Pro-
gram cycle in the flash bank has commenced, the SRAM
bank can be accessed for Read or Write.
©2005 Silicon Storage Technology, Inc.
S71236-04-000
5/05
1
The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc.
MPF+ and ComboMemory are trademarks of Silicon Storage Technology, Inc.
These specifications are subject to change without notice.
1 page  
Multi-Purpose Flash Plus + SRAM ComboMemory
SST32HF1641 / SST32HF1681 / SST32HF3241 / SST32HF3281
SST32HF1621C / SST32HF1641C / SST32HF3241C
Preliminary Specifications
Hardware Block Protection
The SST32HFx1/x1C support bottom hardware block
protection, which protects the bottom 32 KWord block of
the device. The Boot Block address is 000000H-007FFFH.
Program and Erase operations are prevented on the 32
KWord when WP# is low. If WP# is left floating, it is inter-
nally held high via a pull-up resistor, and the Boot Block is
unprotected, enabling Program and Erase operations on
that block.
SRAM Read
The SRAM Read operation of the SST32HFx1/x1C is con-
trolled by OE# and BES1#, both have to be low with WE#
and BES2 high for the system to obtain data from the out-
puts. BES1# and BES2 are used for SRAM bank selection.
OE# is the output control and is used to gate data from the
output pins. The data bus is in high impedance state when
OE# is high. Refer to the Read cycle timing diagram, Fig-
ure 3, for further details.
Hardware Reset (RST#)
The RST# pin provides a hardware method of resetting the
device to read array data. When the RST# pin is held low
for at least TRP, any in-progress operation will terminate and
return to Read mode. When no internal Program/Erase
operation is in progress, a minimum period of TRHR is
required after RST# is driven high before a valid Read can
take place (see Figure 17).
The Erase or Program operation that has been interrupted
needs to be reinitiated after the device resumes normal
operation mode to ensure data integrity.
Flash Software Data Protection (SDP)
The SST32HFx1/x1C provide the JEDEC approved soft-
ware data protection scheme for all flash memory bank
data alteration operations, i.e., Program and Erase. Any
Program operation requires the inclusion of a series of
three-byte sequence. The three byte-load sequence is
used to initiate the Program operation, providing optimal
protection from inadvertent Write operations, e.g., during
the system power-up or power-down. Any Erase operation
requires the inclusion of six-byte load sequence. The
SST32HFx1/x1C devices are shipped with the software
data protection permanently enabled. See Table 5 for the
specific software command codes. During SDP command
sequence, invalid commands will abort the device to Read
mode, within TRC. The contents of DQ15-DQ8 can be VIL or
VIH, but no other value, during any SDP command
sequence.
SRAM Write
The SRAM Write operation of the SST32HFx1/x1C is con-
trolled by WE# and BES1#, both have to be low, BES2
must be high for the system to write to the SRAM. During
the Word-Write operation, the addresses and data are ref-
erenced to the rising edge of either BES1#, WE#, or the
falling edge of BES2 whichever occurs first. The write time
is measured from the last falling edge of BES#1 or WE# or
the rising edge of BES2 to the first rising edge of BES1#, or
WE# or the falling edge of BES2. Refer to the Write cycle
timing diagrams, Figures 4 and 5, for further details.
Product Identification
The Product Identification mode identifies the devices as
the SST32HFx1/x1C and manufacturer as SST. This
mode may be accessed by software operations only.
The hardware device ID Read operation, which is typi-
cally used by programmers, cannot be used on this
device because of the shared lines between flash and
SRAM in the multi-chip package. Therefore, applica-
tion of high voltage to pin A9 may damage this device.
Users may use the software Product Identification opera-
tion to identify the part (i.e., using the device ID) when using
multiple manufacturers in the same socket. For details, see
Tables 4 and 5 for software operation, Figure 14 for the
software ID entry and read timing diagram and Figure 23
for the ID entry command sequence flowchart.
TABLE 2: PRODUCT IDENTIFICATION
Manufacturer’s ID
Device ID
SST32HF16x1x
SST32HF32x1x
Address
0000H
0001H
0001H
Data
BFH
234BH
235BH
T2.2 1236
©2005 Silicon Storage Technology, Inc.
5
S71236-04-000
5/05
5 Page 
Multi-Purpose Flash Plus + SRAM ComboMemory
SST32HF1641 / SST32HF1681 / SST32HF3241 / SST32HF3281
SST32HF1621C / SST32HF1641C / SST32HF3241C
Preliminary Specifications
Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maximum
Stress Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation
of the device at these conditions or conditions greater than those defined in the operational sections of this data
sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.)
Operating Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -20°C to +85°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C
D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5V to VDD1+0.3V
Transient Voltage (<20 ns) on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1.0V to VDD1+1.0V
Package Power Dissipation Capability (TA = 25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W
Surface Mount Solder Reflow Temperature2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C for 10 seconds
Output Short Circuit Current3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
1. VDD = VDDF and VDDS
2. Excluding certain with-Pb 32-PLCC units, all packages are 260°C capable in both non-Pb and with-Pb solder versions.
Certain with-Pb 32-PLCC package types are capable of 240°C for 10 seconds; please consult the factory for the latest information.
3. Outputs shorted for no more than one second. No more than one output shorted at a time.
OPERATING RANGE
Range
Commercial
Extended
Ambient Temp
0°C to +70°C
-20°C to +85°C
VDD
2.7-3.3V
2.7-3.3V
AC CONDITIONS OF TEST
Input Rise/Fall Time . . . . . . . . . . . . . . 5 ns
Output Load . . . . . . . . . . . . . . . . . . . . CL = 30 pF
See Figures 19 and 20
©2005 Silicon Storage Technology, Inc.
11
S71236-04-000
5/05
11 Page | ||
| Páginas | Total 36 Páginas | |
| PDF Descargar | [ Datasheet SST32HF1641.PDF ] | |
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