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PDF SST32HF164 Data sheet ( Hoja de datos )
| Número de pieza | SST32HF164 | |
| Descripción | (SST32HFxxx) Multi-Purpose Flash (MPF) + SRAM ComboMemory | |
| Fabricantes | SST | |
| Logotipo |  |
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Multi-Purpose Flash (MPF) + SRAM ComboMemory
SST32HF802 / SST32HF162 / SST32HF164
FEATURES:
SST32HF802 / 162 / 164MPF (x16) + 1Mb SRAM (x16) ComboMemories
Data Sheet
• MPF + SRAM ComboMemory
– SST32HF802: 512K x16 Flash + 128K x16 SRAM
– SST32HF162: 1M x16 Flash + 128K x16 SRAM
– SST32HF164: 1M x16 Flash + 256K x16 SRAM
• Single 2.7-3.3V Read and Write Operations
• Concurrent Operation
– Read from or write to SRAM while
Erase/Program Flash
• Superior Reliability
– Endurance: 100,000 Cycles (typical)
– Greater than 100 years Data Retention
• Low Power Consumption:
– Active Current: 15 mA (typical) for
Flash or SRAM Read
– Standby Current: 20 µA (typical)
• Flexible Erase Capability
– Uniform 2 KWord sectors
– Uniform 32 KWord size blocks
• Fast Read Access Times:
– Flash: 70 ns and 90 ns
– SRAM: 70 ns and 90 ns
• Latched Address and Data for Flash
• Flash Fast Erase and Word-Program:
– Sector-Erase Time: 18 ms (typical)
– Block-Erase Time: 18 ms (typical)
– Chip-Erase Time: 70 ms (typical)
– Word-Program Time: 14 µs (typical)
– Chip Rewrite Time:
SST32HF802: 8 seconds (typical)
SST32HF162/164: 15 seconds (typical)
• Flash Automatic Erase and Program Timing
– Internal VPP Generation
• Flash End-of-Write Detection
– Toggle Bit
– Data# Polling
• CMOS I/O Compatibility
• JEDEC Standard Command Set
• Package Available
– 48-lead TSOP (12mm x 20mm)
– 48-ball TBGA (10mm x 12mm)
PRODUCT DESCRIPTION
The SST32HF802/162/164 ComboMemory devices inte-
grate a 512K x16 or 1M x16 CMOS flash memory bank
with a 128K x16 or 256K x16 CMOS SRAM memory bank
in a Multi-Chip Package (MCP), manufactured with SST’s
proprietary, high performance SuperFlash technology.
Featuring high performance Word-Program, the flash
memory bank provides a maximum Word-Program time of
14 µsec. The entire flash memory bank can be erased and
programmed word-by-word in typically 8 seconds for the
SST32HF802 and 15 seconds for the SST32HF162/164,
when using interface features such as Toggle Bit or Data#
Polling to indicate the completion of Program operation. To
protect against inadvertent flash write, the SST32HF802/
162/164 devices contain on-chip hardware and software
data protection schemes.The SST32HF802/162/164
devices offer a guaranteed endurance of 10,000 cycles.
Data retention is rated at greater than 100 years.
The SST32HF802/162/164 devices consist of two inde-
pendent memory banks with respective bank enable sig-
nals. The Flash and SRAM memory banks are
superimposed in the same memory address space. Both
memory banks share common address lines, data lines,
WE# and OE#. The memory bank selection is done by
memory bank enable signals. The SRAM bank enable sig-
nal, BES# selects the SRAM bank. The flash memory
©2001 Silicon Storage Technology, Inc.
S71171-05-000 8/01
520
1
bank enable signal, BEF# selects the flash memory bank.
The WE# signal has to be used with Software Data Protec-
tion (SDP) command sequence when controlling the Erase
and Program operations in the flash memory bank. The
SDP command sequence protects the data stored in the
flash memory bank from accidental alteration.
The SST32HF802/162/164 provide the added functionality
of being able to simultaneously read from or write to the
SRAM bank while erasing or programming in the flash
memory bank. The SRAM memory bank can be read or
written while the flash memory bank performs Sector-
Erase, Bank-Erase, or Word-Program concurrently. All
flash memory Erase and Program operations will automati-
cally latch the input address and data signals and complete
the operation in background without further input stimulus
requirement. Once the internally controlled erase or pro-
gram cycle in the flash bank has commenced, the SRAM
bank can be accessed for read or write.
The SST32HF802/162/164 devices are suited for applica-
tions that use both flash memory and SRAM memory to
store code or data. For systems requiring low power and
small form factor, the SST32HF802/162/164 devices signif-
icantly improve performance and reliability, while lowering
power consumption, when compared with multiple chip
solutions. The SST32HF802/162/164 inherently use less
energy during erase and program than alternative flash
The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc.
MPF and ComboMemory are trademarks of Silicon Storage Technology, Inc.
These specifications are subject to change without notice.
1 page  
Multi-Purpose Flash (MPF) + SRAM ComboMemory
SST32HF802 / SST32HF162 / SST32HF164
Data Sheet
FUNCTIONAL BLOCK DIAGRAM
Address Buffers
AMS(1)-A0
UBS#
LBS#
BES#
BEF#
OE#
WE#
Control Logic
SRAM
I/O Buffers
DQ15 - DQ8
DQ7 - DQ0
Address Buffers
& Latches
SuperFlash
Memory
520 ILL B1.1
SST32HF162/164
A15
A14
A13
A12
A11
A10
A9
A8
A19
NC
WE#
VDDS
BES#
UBS#
LBS#
A18
A17
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Standard Pinout
Top View
Die Up
SST32HF162/164
48 A16
47 NC
46 VSS
45 DQ15
44 DQ7
43 DQ14
42 DQ6
41 DQ13
40 DQ5
39 DQ12
38 DQ4
37 VDDF
36 DQ11
35 DQ3
34 DQ10
33 DQ2
32 DQ9
31 DQ1
30 DQ8
29 DQ0
28 OE#
27 VSS
26 BEF#
25 A0
520 ILL F01b.1
FIGURE 1: PIN ASSIGNMENTS FOR 48-LEAD TSOP (12MM X 20MM)
©2001 Silicon Storage Technology, Inc.
5
S71171-05-000 8/01 520
5 Page 
Multi-Purpose Flash (MPF) + SRAM ComboMemory
SST32HF802 / SST32HF162 / SST32HF164
Data Sheet
TABLE 11: FLASH READ CYCLE TIMING PARAMETERS
SST32HF802/162/164-70 SST32HF802/162/164-90
Symbol
TRC
TBE
TAA
TOE
TBLZ1
TOLZ1
TBHZ1
TOHZ1
TOH1
Parameter
Read Cycle Time
Bank Enable Access Time
Address Access Time
Output Enable Access Time
BEF# Low to Active Output
OE# Low to Active Output
BEF# High to High-Z Output
OE# High to High-Z Output
Output Hold from Address Change
Min Max Min Max
70 90
70 90
70 90
35 45
00
00
20 30
20 30
00
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
T11.1 520
TABLE 12: FLASH PROGRAM/ERASE CYCLE TIMING PARAMETERS
Symbol
TBP
TAS
TAH
TBS
TBH
TOES
TOEH
TBPW
TWP
TWPH
TBPH
TDS
TDH
TIDA
TSE
TBE
TSCE
Parameter
Word-Program Time
Address Setup Time
Address Hold Time
WE# and BEF# Setup Time
WE# and BEF# Hold Time
OE# High Setup Time
OE# High Hold Time
BEF# Pulse Width
WE# Pulse Width
WE# Pulse Width High
BEF# Pulse Width High
Data Setup Time
Data Hold Time
Software ID Access and Exit Time
Sector-Erase
Block-Erase
Chip-Erase
Min
0
30
0
0
0
10
40
40
30
30
30
0
Max
20
150
25
25
100
Units
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ms
ms
T12.0 520
©2001 Silicon Storage Technology, Inc.
11
S71171-05-000 8/01 520
11 Page | ||
| Páginas | Total 28 Páginas | |
| PDF Descargar | [ Datasheet SST32HF164.PDF ] | |
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