PDF ZL20250 Data sheet ( Hoja de datos )

Número de pieza	ZL20250
Descripción	2.5G Multimode Transceiver
Fabricantes	Zarlink Semiconductor
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No Preview Available ! www.DataSheet4U.com Features • Quad Band GSM (800/900/1800/1900 MHz) Compatible • Dual Band IS136 (800/1900 MHz) Compatible • GPRS Class 12 and EDGE Capable • Fully Integrated Dual Band Transceiver • Receive - IF to Baseband I and Q • Transmit - Baseband I / Q to RF • Integrated Filters • FM Demodulator • RF and IF Synthesizers • Fully Programmable via serial bus • 3 Volt operation • Small scale package Applications • GAIT IS136/GSM/EDGE Mobile Telephones • Dual Band (850/PCS1900) TDMA/AMPS Mobile Telephones • Cellular 850MHz TDMA/AMPS Mobile Telephones • PCS1900 TDMA Mobile Telephones • 2.5G World Phones - Quad Band (850/900/1800/1900) • Cellular Telematic Systems ZL20250 2.5G Multimode Transceiver Data Sheet September 2003 Ordering Information ZL20250/LCE (Tubes) 56 pin QFN ZL20250/LCF (Tape and Reel) 56 pin QFN -40°C to +85°C Description The ZL20250 is a fully integrated transceiver for multimode IS136/GSM/GPRS/EDGE handsets. The dual IF inputs to the receive path are amplified and down-converted to baseband I and Q signals. Gain control and baseband filtering are provided. A FM demodulator is also provided where AMPS compatibility is required. The transmit path consists of a quadrature modulator, gain control at IF and up-conversion to RF. Dual band RF outputs are provided. ZL20250 also includes a fractional N RF synthesizer and two IF synthesizers to provide all local oscillator signals required. Flexible programming is provided via a 3 wire serial bus. Additional control pins allow accurate timing control when switching between modes. GSM/EDGE IS136 UHF LO O/P UHF VCO 900 MHz Tx 1900 MHz Tx 90° Rx VHF PLL UHF PLL FM Demod Tx VHF PLL Serial Interface Control Rx I Rx Q FM RSSI LOCK DET Tx I IQ Mod Tx Q Tx IF Filter (Opt) Figure 1 - Block Diagram 1 Zarlink Semiconductor Inc. Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2003, Zarlink Semiconductor Inc. All Rights Reserved. 1 page ZL20250 Data Sheet Table of Contents 1.0 General Description ......................................................................................................................................... 8 1.1 Receive Path ............................................................................................................................................... 9 1.1.1 IS136.................................................................................................................................................. 9 1.1.2 AMPS FM......................................................................................................................................... 11 1.1.3 GSM ................................................................................................................................................. 14 1.2 Transmit..................................................................................................................................................... 16 1.3 UHF LO and Frequency Doubler............................................................................................................... 19 1.4 UHF Frequency Synthesizer ..................................................................................................................... 19 1.5 VHF Frequency Synthesizer...................................................................................................................... 22 1.6 Internal Clock Generation.......................................................................................................................... 23 1.7 VHF VCO................................................................................................................................................... 23 1.8 Power Supply Connections ....................................................................................................................... 24 2.0 Programming and Control ............................................................................................................................ 25 2.1 Power Control Registers - Address 0 to 3 ................................................................................................. 25 2.1.1 Power Control Modes - TDMA (GSM and IS136) ............................................................................ 27 2.1.2 Power Control Modes - AMPS ......................................................................................................... 28 2.2 Operating Register Address 4 ................................................................................................................... 29 2.3 Synthesizer Register - Address 5 .............................................................................................................. 33 2.3.1 UHF PLL and LO.............................................................................................................................. 33 2.3.2 UHF PLL Charge Pump Current ...................................................................................................... 34 2.3.3 Receive LO Set Up .......................................................................................................................... 34 2.3.4 Transmit LO Set Up ......................................................................................................................... 35 2.4 Control Register - Address 6 ..................................................................................................................... 35 2.4.1 IS136 Baseband Gain ...................................................................................................................... 35 2.4.2 TCXO Reference Selection............................................................................................................. 36 2.4.3 Discriminator Output Filtering........................................................................................................... 36 2.4.4 Transmit baseband Gain.................................................................................................................. 37 2.4.5 Mode Control.................................................................................................................................... 37 2.5 GSM/EDGE Baseband Control Register - Address 7................................................................................ 37 2.5.1 Q Channel Gain Adjust .................................................................................................................... 38 2.5.2 Baseband Offset Correction............................................................................................................. 38 2.6 Test Mode Register - Address 8................................................................................................................ 38 2.7 UHF PLL Divider Programming Register - Address 9 ............................................................................... 39 2.8 UHF PLL Reference Divider and Fractional N Programming Register - Address 10 ................................ 39 2.9 Receive VHF PLL Divider Programming Register - Address 11 ............................................................... 39 2.10 Receive VHF PLL Reference Divider Programming Register - Address 12............................................ 40 2.11 Transmit VHF PLL Divider Programming Register - Address 13 ............................................................ 40 2.12 Transmit VHF PLL Reference Divider Programming Register Address 14 ............................................. 40 2.13 PLL Lock Detect & Fractional N Compensation Programming Register Address 15 .............................. 40 2.13.1 Fractional N Compensation............................................................................................................ 41 2.13.2 PLL Lock detect counters............................................................................................................... 41 3.0 Absolute Maximum Ratings .......................................................................................................................... 41 4.0 Operating Conditions .................................................................................................................................... 41 5.0 Electrical Characteristics .............................................................................................................................. 43 6.0 Typical Performance Curves ........................................................................................................................ 51 6.1 Receive...................................................................................................................................................... 51 6.2 Transmit..................................................................................................................................................... 52 5 Zarlink Semiconductor Inc. 5 Page ZL20250 Data Sheet 1.1.2 AMPS FM FM demodulation can be performed using the I and Q baseband signals if supported by the baseband. However the ZL20250 also contains an FM demodulator, the AMPS receive signal path using this mode is shown in detail in Figure 5 and performance for each stage is summarized in the following table. Circuit Block IF Input (IF0) AGC Amplifier Quadrature Down-converter Anti-alias filter Band Pass Filter Limiter FM Discriminator Baseband filter 2 (I Channel) Baseband filter 1 (I Channel) Baseband filter 1 (Q Channel) Baseband filter 2 (Q Channel) FM Output Gain (dB) Filter Bandwidth (If Applicable) Description Differential IF input stage 26 max AGC Amplifier - Gain control range 90dB. Includes IF input stage gain. Down-conversion to 60kHz IF 230 kHz Low pass Butterworth 73 +/- 16 kHz Switched capacitor polyphase Chebyshev. Also provides typically 30dB image rejection. Centre frequency = 60 kHz. Clock frequency 1.44 MHz and 720 kHz. Provides limited output to discriminator. Also provides RSSI output. Digital FM discriminator 30 kHz Smoothing filter. Low pass Butterworth. Provides filtering of FM discriminator output. 25 kHz Switched capacitor low pass Chebyshev. Clock frequency = 240 kHz. Provides additional filtering of discriminator output. Selected using PDF and LPC bits 25 kHz Switched capacitor low pass Chebyshev. Clock frequency = 240 kHz. Provides additional filtering of discriminator output. Selected using PDF and LPC bits 60kHz Smoothing filter. Low pass Butterworth. Provides filtering of FM discriminator output. 30kHz Configured using external components as bandpass filter. Table 2 - AMPS FM Receive Gain and Filter Distribution The signal path is initially the same as for IS136 with the down conversion to 60 kHz and channel filtering in the bandpass filter. In FM mode however, the baseband I and Q output stages are disabled, and the 60 kHz IF signal from the bandpass filter is input to a limiting amplifier and FM discriminator. The FM discriminator consists of a shift register acting as a delay line. The output of the discriminator is a digital signal which must then be filtered to recover the audio signal. The discriminator output is therefore routed through the baseband I and Q filters. The default condition is to use the cascaded I and Q smoothing filters (baseband filter 2) with the cut-off frequency set to 30kHz. This connection is automatically selected when programming FM mode. There is an option to use the cascaded switched capacitor filters (baseband filter 1) with the cut off frequency set to 25 kHz to provide extra filtering. These filters are selected using the PDF and LPC bits in control register 6 and are inserted between the smoothing filters as shown in Figure 5. The final output stage uses external feedback components to provide a bandpass filter with a bandwidth of at least 300 Hz to 10 KHz to cover the demodulated audio and control signals. The feedback components can be modified to change the output level to optimise compatibility with baseband. A RSSI output is provided. This is a full wave rectified output of the 60 kHz IF and therefore has a high 120 kHz content. This requires an external low pass filter - typically 10kohm and 2.7nF. There is a trade-off between settling 11 Zarlink Semiconductor Inc. 11 Page

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