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K8D1716UBC Schematic ( PDF Datasheet ) - Samsung semiconductor

Teilenummer K8D1716UBC
Beschreibung 16M Bit (2M x8/1M x16) Dual Bank NOR Flash Memory
Hersteller Samsung semiconductor
Logo Samsung semiconductor Logo 




Gesamt 30 Seiten
K8D1716UBC Datasheet, Funktion
www.DataSheet4U.com
K8D1716UTC / K8D1716UBC
FLASH MEMORY
Document Title
16M Bit (2M x8/1M x16) Dual Bank NOR Flash Memory
Revision History
Revision No. History
0.0 Initial Draft
0.1 Support 48TSOP1 Lead Free Package
0.2 Support 48FBGA Leaded/Lead Free Package
1.0 Specification finalized
Draft Date
July 25, 2004
Sep 16, 2004
Nov 29, 2004
Dec 16, 2004
Remark
Advance
Preliminary
Preliminary
1 Revision 1.0
December 2004






K8D1716UBC Datasheet, Funktion
K8D1716UTC / K8D1716UBC
FLASH MEMORY
Table 5. Bottom Boot Block Address (K8D1716UB)
K8D1716UT
Block
A19 A18 A17 A16 A15 A14 A13 A12
Block Size
(KW/KB)
Address Range
Word Mode
Byte Mode
BA38 1 1 1 1 1 X X X
BA37 1 1 1 1 0 X X X
32 / 64
32 / 64
F8000H-FFFFFH
F0000H-F7FFFH
1F0000H-1FFFFFH
1E0000H-1EFFFFH
BA36 1 1 1 0 1 X X X
BA35 1 1 1 0 0 X X X
BA34 1 1 0 1 1 X X X
32 / 64
32 / 64
32 / 64
E8000H-EFFFFH
E0000H-E7FFFH
D8000H-DFFFFH
1D0000H-1DFFFFH
1C0000H-1CFFFFH
1B0000H-1BFFFFH
Bank2
BA33 1 1 0 1 0 X X X
BA32 1 1 0 0 1 X X X
BA31 1 1 0 0 0 X X X
BA30 1 0 1 1 1 X X X
BA29 1 0 1 1 0 X X X
BA28 1 0 1 0 1 X X X
32 / 64
32 / 64
32 / 64
32 / 64
32 / 64
32 / 64
D0000H-D7FFFH
C8000H-CFFFFH
C0000H-C7FFFH
B8000H-BFFFFH
B0000H-B7FFFH
A8000H-AFFFFH
1A0000H-1AFFFFH
190000H-19FFFFH
180000H-18FFFFH
170000H-17FFFFH
160000H-16FFFFH
150000H-15FFFFH
BA27 1 0 1 0 0 X X X
BA26 1 0 0 1 1 X X X
BA25 1 0 0 1 0 X X X
BA24 1 0 0 0 1 X X X
BA23 1 0 0 0 0 X X X
BA22 0 1 1 1 1 X X X
BA21 0 1 1 1 0 X X X
BA20 0 1 1 0 1 X X X
BA19 0 1 1 0 0 X X X
BA18 0 1 0 1 1 X X X
BA17 0 1 0 1 0 X X X
BA16 0 1 0 0 1 X X X
BA15 0 1 0 0 0 X X X
BA14 0 0 1 1 1 X X X
32 / 64
32 / 64
32 / 64
32 / 64
32 / 64
32 / 64
32 / 64
32 / 64
32 / 64
32 / 64
32 / 64
32 / 64
32 / 64
32 / 64
A0000H-A7FFFH
98000H-9FFFFH
90000H-97FFFH
88000H-8FFFFH
80000H-87FFFH
78000H-7FFFFH
70000H-77FFFH
68000H-6FFFFH
60000H-67FFFH
58000H-5FFFFH
50000H-57FFFH
48000H-4FFFFH
40000H-47FFFH
38000H-3FFFFH
140000H-14FFFFH
130000H-13FFFFH
120000H-12FFFFH
110000H-11FFFFH
100000H-10FFFFH
0F0000H-0FFFFFH
0E0000H-0EFFFFH
0D0000H-0DFFFFH
0C0000H-0CFFFFH
0B0000H-0BFFFFH
0A0000H-0AFFFFH
090000H-09FFFFH
080000H-08FFFFH
070000H-07FFFFH
Bank1
BA13 0 0 1 1 0 X X X
BA12 0 0 1 0 1 X X X
BA11 0 0 1 0 0 X X X
32 / 64
32 / 64
32 / 64
30000H-37FFFH
28000H-2FFFFH
20000H-27FFFH
060000H-06FFFFH
050000H-05FFFFH
040000H-04FFFFH
BA10 0 0 0 1 1 X X X
BA9 0 0 0 1 0 X X X
BA8 0 0 0 0 1 X X X
32 / 64
32 / 64
32 / 64
18000H-1FFFFH
10000H-17FFFH
08000H-0FFFFH
030000H-03FFFFH
020000H-02FFFFH
010000H-01FFFFH
BA7 0 0 0 0 0 1 1 1
4/8
07000H-07FFFH 00E000H-00FFFFH
BA6 0 0 0 0 0 1 1 0
4/8
06000H-06FFFH 00C000H-00DFFFH
BA5 0 0 0 0 0 1 0 1
4/8
05000H-05FFFH 00A000H-00BFFFH
BA4 0 0 0 0 0 1 0 0
4/8
04000H-04FFFH 008000H-009FFFH
BA3 0 0 0 0 0 0 1 1
4/8
03000H-03FFFH 006000H-007FFFH
BA2 0 0 0 0 0 0 1 0
4/8
02000H-02FFFH 004000H-005FFFH
BA1 0 0 0 0 0 0 0 1
4/8
01000H-01FFFH 002000H-003FFFH
BA0 0 0 0 0 0 0 0 0
4/8
00000H-00FFFH 000000H-001FFFH
Table 6. Secode Block Addresses for Bottom Boot Devices
Device
Block Address
A19-A12
Block
Size
K8D1716UB
00000xxx
64/32
(X8)
Address Range
000000H-00FFFFH
(X16)
Address Range
00000H-07FFFH
6 Revision 1.0
December 2004

6 Page









K8D1716UBC pdf, datenblatt
K8D1716UTC / K8D1716UBC
FLASH MEMORY
Unlock Bypass
The K8D1716U provides the unlock bypass mode to save its program time for program operation. The mode is invoked by the unlock
bypass command sequence. Then, the unlock bypass program command sequence is required to program the device.
Unlike the standard program command sequence that contains four bus cycles, the unlock bypass program command sequence
comprises only two bus cycles.
The unlock bypass mode is engaged by issuing the unlock bypass command sequence which is comprised of three bus cycles. Writ-
ing first two unlock cycles is followed by a third cycle containing the unlock bypass command (20H). Once the device is in the unlock
bypass mode, the unlock bypass program command sequence is necessary to program in this mode. The unlock bypass program
command sequence is comprised of only two bus cycles; writing the unlock bypass program command (A0H) is followed by the pro-
gram address and data. This command sequence is the only valid one for programming the device in the unlock bypass mode.
The unlock bypass reset command sequence is the only valid command sequence to exit the unlock bypass mode. The unlock
bypass reset command sequence consists of two bus cycles. The first cycle must contain the data (90H). The second cycle contains
only the data (00H). Then, the device returns to the read mode.
Chip Erase
To erase a chip is to write 1s into the entire memory array by executing the Internal Erase Routine. The Chip Erase requires six bus
cycles to write the command sequence. The erase set-up command is written after first two "unlock" cycles. Then, there are two
more write cycles prior to writing the chip erase command. The Internal Erase Routine automatically pre-programs and verifies the
entire memory for an all zero data pattern prior to erasing. The automatic erase begins on the rising edge of the last WE or CE pulse
in the command sequence and terminates when DQ7 is "1". After that the device returns to the read mode.
WE
A19A0(x16)/
A19A-1(x8)
DQ15-DQ0
RY/BY
555H/
AAAH
2AAH/
555H
555H/
AAAH
555H
AAAH
2AAH/
555H
555H/
AAAH
AAH
55H
80H
AAH
55H
10H
Chip Erase
Start
Figure 5. Chip Erase Command Sequence
Block Erase
To erase a block is to write 1s into the desired memory block by executing the Internal Erase Routine. The Block Erase requires six
bus cycles to write the command sequence shown in Table 8. After the first two "unlock" cycles, the erase setup command (80H) is
written at the third cycle. Then there are two more "unlock" cycles followed by the Block Erase command. The Internal Erase Routine
automatically pre-programs and verifies the entire memory prior to erasing it. The block address is latched on the falling edge of WE
or CE, while the Block Erase command is latched on the rising edge of WE or CE.
Multiple blocks can be erased sequentially by writing the six bus-cycle operation in Figure 6. Upon completion of the last cycle for the
Block Erase, additional block address and the Block Erase command (30H) can be written to perform the Multi-Block Erase. An 50µs
(typical) "time window" is required between the Block Erase command writes. The Block Erase command must be written within the
50µs "time window", otherwise the Block Erase command will be ignored. The 50µs "time window" is reset when the falling edge of
the WE occurs within the 50µs of "time window" to latch the Block Erase command. During the 50µs of "time window", any command
other than the Block Erase or the Erase Suspend command written to the device will reset the device to read mode. After the 50µs of
"time window", the Block Erase command will initiate the Internal Erase Routine to erase the selected blocks. Any Block Erase
address and command following the exceeded "time window" may or may not be accepted. No other commands will be recognized
except the Erase Suspend command during Block Erase operation.
12 Revision 1.0
December 2004

12 Page





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