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PDF MB90867E Data sheet ( Hoja de datos )
| Número de pieza | MB90867E | |
| Descripción | (MB90860E Series) 16-bit Proprietary Microcontroller CMOS | |
| Fabricantes | Fujitsu Media Devices | |
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FUJITSU SEMICONDUCTOR
DATA SHEET
DS07-13748-1E
16-bit Proprietary Microcontroller
CMOS
F2MC-16LX MB90860E Series
MB90867E(S), MB90F867E(S),
MB90V340E-101/102
■ DESCRIPTION
MB90860E-series with Flash ROM is especially designed for automotive and other industrial applications. With
the new 0.35 µm CMOS technology, Fujitsu now offers on-chip Flash ROM program memory up to 512 Kbytes.
The power supply (3 V) is supplied to the internal MCU core from an internal regulator circuit. This creates a
major advantage in terms of EMI and power consumption.
The internal PLL clock frequency multiplier provides an internal 42 ns instruction cycle time from an external
4 MHz clock.
The unit features an 8 channel Output Compare Unit and 8 channel Input Capture Unit with 2 separate 16-bit free
running timers. 4 UARTs constitute additional functionality for communication purposes.
Note : F2MC is the abbreviation of FUJITSU Flexible Microcontroller.
Be sure to refer to the “Check Sheet” for the latest cautions on development.
“Check Sheet” is seen at the following support page
URL : http://www.fujitsu.com/global/services/microelectronics/product/micom/support/index.html
“Check Sheet” lists the minimal requirement items to be checked to prevent problems beforehand in system
development.
Copyright©2006 FUJITSU LIMITED All rights reserved
1 page  
MB90860E Series
(Continued)
Part Number
Parameter
MB90867E(S)
MB90F867E(S)
MB90V340E-101/102
8/16-bit
programmable pulse
generator
(8 channels)
Supports 8-bit and 16-bit operation modes
Sixteen 8-bit reload counters
Sixteen 8-bit reload registers for L pulse width
Sixteen 8-bit reload registers for H pulse width
A pair of 8-bit reload counters can be configured as one 16-bit reload counter or as
8-bit prescaler plus 8-bit reload counter
Operation clock freq. : fsys, fsys/21, fsys/22, fsys/23, fsys/24 or 128 µs@fosc = 4 MHz
(fsys = Machine clock frequency, fosc = Oscillation clock frequency)
CAN interface
⎯ 3 channels
External interrupt
(16 channels)
Can be used rising edge, falling edge, starting up by H/L level input, external interrupt,
expanded intelligent I/O services (EI2OS) and DMA
D/A converter
⎯ 2 channels
Up to 100 kHz
sub clock for low
power operation
Devices without ‘S’-suffix
Only for MB90V340E-
102
I/O ports
Virtually all external pins can be used as general purpose I/O port
All push-pull outputs
Bit-wise settable as input/output or peripheral signal
Settable in pin-wise of 8 as CMOS schmitt trigger/automotive inputs (default)
TTL input level settable for external bus (32-pin only for external bus)
Flash memory
Supports automatic programming, Embedded AlgorithmTM*2
Write/Erase/Erase-Suspend/Resume commands
A flag indicating completion of the algorithm
Number of erase cycles : 10,000 times
Data retention time : 20 years
Boot block configuration
Erase can be performed on each block
Block protection with external programming voltage
Flash Security Feature for protecting the content of the Flash
⎯
*1 : It is setting of Jumper switch (TOOL VCC) when Emulator (MB2147-01) is used.
Please refer to the Emulator hardware manual about details.
*2 : Embedded Algorithm is a trade mark of Advanced Micro Devices Inc.
5
5 Page 
MB90860E Series
Pin No.
QFP100*1 LQFP100*2
97
10 8
11 9
12 10
13, 14
11, 12
15 13
16 14
17 15
18 16
Pin name
P34
HRQ
OUT4
P35
HAK
OUT5
P36
RDY
OUT6
P37
CLK
OUT7
P40, P41
X0A , X1A
VCC
VSS
C
P42
IN6
INT9R
I/O
Circuit
type*3
Function
General purpose I/O pin. The register can be set to select
whether to use a pull-up resistor. This function is enabled either
in single-chip mode or with the hold function disabled.
G Hold request input pin. This function is enabled when both the
external bus and the hold function are enabled.
Waveform output pin for output compare 4.
General purpose I/O pin. The register can be set to select
whether to use a pull-up resistor. This function is enabled either
in single-chip mode or with the hold function disabled.
G Hold acknowledge output pin. This function is enabled when
both the external bus and the hold function are enabled.
Waveform output pin for output compare 5.
General purpose I/O pin. The register can be set to select
whether to use a pull-up resistor. This function is enabled either
in single-chip mode or with the external ready function disabled.
G External ready input pin. This function is enabled when both the
external bus and the external ready function are enabled.
Waveform output pin for output compare 6.
General purpose I/O pin. The register can be set to select
whether to use a pull-up resistor. This function is enabled either
in single-chip mode or with the clock output disabled.
G Clock output pin. This function is enabled when both the
external bus and clock output are enabled.
Waveform output pin for output compare 7.
F
General purpose I/O pins.
(devices with S-suffix)
B
Input pins for sub-clock
(devices without S-suffix)
⎯ Power (3.5 V to 5.5 V) input pin
⎯ GND pin
This is the power supply stabilization capacitor pin. It should be
K connected to a higher than or equal to 0.1 µF ceramic
capacitor.
General purpose I/O pin.
F Trigger input pin for input capture 6.
External interrupt request input pin (sub)
(Continued)
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet MB90867E.PDF ] | |
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