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PDF TSA1204 Data sheet ( Hoja de datos )
| Número de pieza | TSA1204 | |
| Descripción | A/D CONVERTER | |
| Fabricantes | ST Microelectronics | |
| Logotipo |  |
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TSA1204
DUAL-CHANNEL, 12-BIT, 20MSPS, 120mW A/D CONVERTER
s 0.5Msps to 20Msps sampling frequency
s Adaptive power consumption: 120mW @
20Msps, 95mW@10Msps
s Single supply voltage: 2.5V
Independent supply for CMOS output stage
with 2.5V/3.3V capability
s ENOB=11.2 @ Nyquist
s SFDR= -81.5 dBc @ Nyquist
s 1GHz analog bandwidth Track-and-Hold
s Common clocking between channels
s Dual simultaneous Sample and Hold inputs
s Multiplexed outputs
s Built-in reference voltage with external bias
capability.
DESCRIPTION
The TSA1204 is a new generation of high speed,
dual-channel Analog to Digital converter pro-
cessed in a mainstream 0.25µm CMOS technolo-
gy yielding high performances and very low power
consumption.
The TSA1204 is specifically designed for applica-
tions requiring very low noise floor, high SFDR
and good isolation between channels. It is based
on a pipeline structure and digital error correction
to provide excellent static linearity and over 11.2
effective bits at Fs=20Msps, and Fin=10MHz.
For each channel, a voltage reference is integrat-
ed to simplify the design and minimize external
components. It is nevertheless possible to use the
circuit with external references.
Each ADC outputs are multiplexed in a common
bus with small number of pins. A tri-state capabili-
ty is available for the outputs, allowing chip selec-
tion. The inputs of the ADC must be differentially
driven.
The TSA1204 is available in extended (-40 to
+85°C) temperature range, in a small 48 pins
TQFP package.
APPLICATIONS
s Medical imaging and ultrasound
s 3G base station
s I/Q signal processing applications
s High speed data acquisition system
s Portable instrumentation
ORDER CODE
Part Number
Temperature
Range
TSA1204IF
TSA1204IFT
EVAL1204/BA
-40°C to +85°C
-40°C to +85°C
February 2003
Package Conditioning Marking
TQFP48
Tray
TQFP48 Tape & Reel
Evaluation board
SA1204I
SA1204I
PIN CONNECTIONS (top view)
index
corner
AGND 1
INI 2
AGND 3
INIB 4
AGND 5
IPOL 6
AVCCB 7
AGND 8
INQ 9
AGND 10
INBQ 11
AGND 12
48 47 46 45 44 43 42 41 40 39 38 37
36 D2
35 D3
34 D4
33 D5
32 D6
TSA1204
31 D7
30 D8
29 D9
28 D10
27 D11(MSB)
26 VCCBE
25 GNDBE
13 14 15 16 17 18 19 20 21 22 23 24
BLOCK DIAGRAM
+2.5V/3.3V
CLK SELECT OEB VCCBE
VINI
VINBI
VINCMI
VREFPI
VREFMI
IPOL
VREFPQ
VREFMQ
VINCMQ
VINQ
VINBQ
AD 12
I channel
common mode
REF I
Polar.
REF Q
common mode
AD 12
Q channel
Timing
12
M 12
12 D0
U Buffers
TO
X D11
12
GND
GNDBE
PACKAGE
7 × 7 mm TQFP48
1/20
1 page  
TSA1204
Symbol
VREFPI
VREFPQ
VREFMI
VREFMQ
INCMI
INCMQ
Parameter
Forced top voltage reference 1)
Forced bottom reference voltage 1)
Forced input common mode voltage
Min
Typ
Max
Unit
0.96
1.4 V
0 0.4 V
0.2 1 V
1) Condition VRefP-VRefM>0.3V
ELECTRICAL CHARACTERISTICS
AVCC = DVCC = VCCB = 2.5V, Fs= 20Msps, Fin=2MHz, Vin@ -1dBFS, VREFP=1.0V, VREFM=0V
Tamb = 25°C (unless otherwise specified)
ANALOG INPUTS
Symbol
Parameter
Test conditions
VIN-VINB Full scale reference voltage
Differential inputs mandatory
Cin Input capacitance
Req Equivalent input resistor
BW Analog Input Bandwidth
Vin@Full Scale, Fs=20Msps
ERB Effective Resolution Bandwidth
Min Typ Max Unit
1.1 2.0 2.8 Vpp
7.0 pF
3 KΩ
1000
MHz
70 MHz
DIGITAL INPUTS AND OUTPUTS
Symbol
Parameter
Clock and Select inputs
VIL Logic "0" voltage
VIH Logic "1" voltage
OEB input
VIL Logic "0" voltage
Test conditions
VIH Logic "1" voltage
Digital Outputs
VOL Logic "0" voltage
Iol=10µA
VOH Logic "1" voltage
Ioh=10µA
IOZ High Impedance leakage current OEB set to VIH
CL Output Load Capacitance
Min Typ Max Unit
0 0.8
2.0 2.5
V
V
0
0.25 x
VCCBE
0.75 x
VCCBE
VCCBE
V
V
0
0.1 x
VCCBE
0.9 x
VCCBE
VCCBE
-1.7 1.7
15
V
V
µA
pF
5/20
5 Page 
TSA1204
Linearity vs. Duty Cycle
Fs=20MSPS; Icca=40mA; Fin=5MHz
100
90
80
70
60
50
40
45
ENOB_I
ENOB_Q
SNR_I SINAD_I
SNR_Q SINAD_Q
47 49 51 53
Positive Duty Cycle (%)
12
11.5
11
10.5
10
9.5
9
8.5
8
7.5
7
55
Distortion vs. Duty Cycle
Fs=20MSPS; Icca=40mA; Fin=5MHz
-40
-50
-60
-70
-80
-90
-100
-110
-120
45
SFDR_Q
THD_Q
SFDR_I THD_I
47 49 51 53
Positive Duty Cycle (%)
55
Single-tone 8K FFT at 20Msps - I Channel
Fin=5MHz; Icca=40mA, Vin@-1dBFS
0
-20
-40
-60
-80
-100
-120
-140
123456789
Frequency (MHz)
Dual-tone 8K FFT at 20Msps - I Channel
Fin1=9.7MHz; Fin2=10.7MHz; Icca=40mA, Vin1@-7dBFS; Vin2@-7dBFS; IMD=-76dBc
0
-20
-40
-60
-80
-100
-120
-140
123456789
Frequency (MHz)
10
10
11/20
11 Page | ||
| Páginas | Total 20 Páginas | |
| PDF Descargar | [ Datasheet TSA1204.PDF ] | |
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