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PDF TSA1005 Data sheet ( Hoja de datos )

Número de pieza TSA1005
Descripción A/D CONVERTER
Fabricantes ST Microelectronics　
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No Preview Available ! TSA1005 Hoja de datos, Descripción, Manual

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TSA1005
DUAL-CHANNEL, 10-BIT, 20/40MSPS A/D CONVERTER
s 10-bit, dual-channel A/D converter in deep
submicron CMOS technology, 20/40Msps
s Single supply voltage: 2.5V
Independent supply for CMOS output stage
with 2.5V/3.3V capability
s ENOB=9.5 @ 20Msps, ENOB=9.2 @
40Msps, Fin=10MHz
s SFDR typically up to 62.5dB @ 40Msps,
Fin=10MHz.
s 1GHz analog bandwidth Track-and-Hold
s Common clocking between channels
s Multiplexed outputs
DESCRIPTION
The TSA1005 belongs to a new generation of high
speed, dual-channel Analog to Digital converters,
processed in a mainstream 0.25 µm CMOS tech-
nology and yielding high performances.
The TSA1005 is specifically designed for applica-
tions requiring a very low noise floor, high SFDR
and good isolation between channels. It is based
on a pipeline structure and digital error correction,
providing high static linearity at 20/40 Msp, and
Fin = 10 MHz.
For each channel, a voltage reference is integrat-
ed to simplify the design and minimize external
components. It is nevertheless possible to use the
circuit with external references.
Each ADC output is multiplexed on a common bus
with small number of pins. A tri-state capability is
available for the output signals, allowing for chip
selection. The input signals of the ADC must be
differentially driven.
The TSA1005 is supports an extended (0 to
+85°C) temperature range, and is available in the
small 48-pin TQFP package.
APPLICATIONS
s Medical imaging and ultrasound
s I/Q signal processing applications
s High speed data acquisition system
s Portable instrumentation
s High resolution fax and scanners
ORDER CODE
Part Number
TSA1005-20IF
TSA1005-20IFT
TSA1005I-40IF
TSA1005-40IFT
EVAL1005-20/BA
EVAL1005-40/BA
June 2003
Temperature
Range
Status
-40°C to +85°C
-40°C to +85°C
0°C to +85°C
0°C to +85°C
Sample
Sample
Production
Production
Evaluation board
Conditioning
Tray
Tape & Reel
Tray
Tape & Reel
PIN CONNECTIONS (top view)
index
corner
AGND 1
INI 2
AGND 3
INIB 4
AGND 5
IPOL 6
AVCCB 7
AGND 8
INQ 9
AGND 10
INBQ 11
AGND 12
48 47 46 45 44 43 42 41 40 39 38 37
36 D0(LSB)
35 D1
34 D2
33 D3
32 D4
TSA1005
31 D5
30 D6
29 D7
28 D8
27 D9(MSB)
26 VCCBE
25 GNDBE
13 14 15 16 17 18 19 20 21 22 23 24
BLOCK DIAGRAM
+2.5V/3.3V
CLK SELECT OEB
VCCBE
VINI
VINBI
VINCMI
VREFPI
VREFMI
IPOL
VREFPQ
VREFMQ
VINCMQ
VINQ
VINBQ
AD 10
I channel
common mode
REF I
Polar.
REF Q
common mode
AD 10
Q channel
Timing
10
M 10
10 D0
U Buffers
TO
X D9
10
GND
GNDBE
PACKAGE
7 × 7 mm TQFP48
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1 page




TSA1005 pdf
TSA1005
CONDITIONS
AVCC = DVCC = VCCB = 2.5V, Fs= 20/40Msps, Fin=2MHz, Vin@ -1dBFS, VREFM=0V
Tamb = 25°C (unless otherwise specified)
ANALOG INPUTS
Symbol
Parameter
VIN-VINB Full scale reference voltage
Cin Input capacitance
Req Equivalent input resistor
Analog Input Bandwidth
BW
Vin Full scale, Fs max
ERB Effective Resolution Bandwidth
1 Preliminary data
DIGITAL INPUTS AND OUTPUTS
TSA1005-20(1)
Min.
1.1
Typ.
2.0
7.0
3.3
Max.
2.8
1000
70
TSA1005-40
Min.
1.1
Typ.
2.0
7
1.6
Max.
2.8
1000
70
Unit
Vpp
pF
KΩ
MHz
MHz
Symbol
Parameter
Clock and Select inputs
VIL Logic "0" voltage
VIH Logic "1" voltage
OEB input
VIL Logic "0" voltage
Test conditions
VIH Logic "1" voltage
Digital Outputs
VOL Logic "0" voltage
Iol=10µA
VOH Logic "1" voltage
Ioh=10µA
IOZ High Impedance leakage current OEB set to VIH
CL Output Load Capacitance
Min Typ Max Unit
0 0.8
2.0 2.5
V
V
0 0.25 x
VCCBE
0.75 x VCCBE
VCCBE
V
V
0 0.1 x
VCCBE
0.9 x VCCBE
VCCBE
-1.67
0
1.67
15
V
V
µA
pF
REFERENCE VOLTAGE
Symbol
Parameter
VREFPI
VREFPQ
VINCMI
VINCMQ
Top internal reference voltage
Input common mode voltage
TSA1005-20(1)
Min. Typ. Max.
0.81 0.88 0.94
TSA1005-40
Min. Typ. Max.
0.81 0.88 0.94
Unit
V
0.41 0.46 0.50 0.41 0.46 0.50
V
5/22

5 Page





TSA1005 arduino
Linearity vs. VCCBE
Fs=20MSPS; Icca=30mA; Fin=10MHz
90
85
80
75
70
65
60
55
50
1.8
ENOB_I
ENOB_Q
SNR_I
SINAD_I
SNR_Q
SINAD_Q
2.3 2.8
VCCBE (V)
3.3
10
9.8
9.6
9.4
9.2
9
8.8
8.6
8.4
8.2
8
Linearity vs. VCCBE
Fs=40MSPS; Icca=45mA; Fin=10MHz
90
85
80
ENOB_I
75
ENOB_Q
70
65 SNR_I
60
SINAD_I
55
50
2.25
SNR_Q
SINAD_Q
2.75
3.25
VCCBE (V)
Linearity vs. Duty Cycle
Fs=20MHz; Icca=30mA; Fin=5MHz
10
9.8
9.6
9.4
9.2
9
8.8
8.6
8.4
8.2
8
90
85
80
75
70
65
60
55
50
45
ENOB_I
ENOB_Q
SNR_I
SINAD_I
SNR_Q
SINAD_Q
47 49 51 53
Positive Duty Cycle (%)
10
9.5
9
8.5
8
7.5
7
55
TSA1005
Distortion vs. VCCBE
Fs=20MSPS; Icca=30mA; Fin=10MHz
-60
-65
-70
-75
-80
-85
-90
-95
-100
1.8
THD_Q
SFDR_Q
THD_I
SFDR_I
2.3 2.8
VCCBE (V)
3.3
Distortion vs. VCCBE
Fs=40MSPS; Icca=45mA; Fin=10MHz
-30
-40
-50
-60
-70
-80
-90 THD_I
-100
-110
-120
2.25
THD_Q
SFDR_Q
SFDR_I
2.75
3.25
VCCBE (V)
Distortion vs. Duty Cycle
Fs=20MHz; Icca=30mA; Fin=5MHz
-40
-50
-60
-70
-80
-90
-100
-110
-120
45
SFDR_Q
THD_Q
SFDR_I THD_I
47 49 51 53
Positive Duty Cycle (%)
55
11/22

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