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Teilenummer | M82C54-2 |
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Beschreibung | CMOS PROGRAMMABLE INTERVAL TIMER | |
Hersteller | OKI electronic | |
Logo | ||
Gesamt 23 Seiten E2O0019-27-X2
www.DataSheet4U.com
¡ Semiconductor¡ Semiconductor
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Previous version: Aug. 1996
MSM82C54-2RS/GS/JS
CMOS PROGRAMMABLE INTERVAL TIMER
GENERAL DESCRIPTION
The MSM82C54-2RS/GS/JS is a programmable universal timer designed for use in
microcomputer systems. Based on silicon gate CMOS technology, it requires a standby current
of only 10 mA (max.) when the chip is in the non-selected state. And during timer operation, the
power consumption is still very low with only 10mA (max.) of current required.
It consists of three independent counters, and can count up to a maximum of 10 MHz. The timer
features six different counter modes, and binary count/BCD count functions. Count values can
be set in byte or word units, and all functions are freely programmable.
FEATURES
• Maximum operating frequency of 10 MHz (VCC=5 V)
• High speed and low power consumption achieved by silicon gate CMOS technology
• Completely static operation
• Three independent 16-bit down-counters
• Status Read Back Command
• Six counter modes available for each counter
• Binary and decimal counting possible
• 24-pin Plastic DIP (DIP24-P-600-2.54): (Product name: MSM82C54-2RS)
• 28-pin Plastic QFJ (QFJ28-P-S450-1.27): (Product name: MSM82C54-2JS)
• 32-pin Plastic SSOP (SSOP32-P-430-1.00-K): (Product name: MSM82C54-2GS-K)
1/23
¡ Semiconductor
TIMING CHART
WriteTiming
A0 - 1
CS
D0 - 7
WR
Read Timing
A0 - 1
CS
RD
D0 - 7
tAW
tSW
tWA
tDW tWD
tWW
tAR tRA
tSR
tRR
tRD
tAD
tDF
Valid
Recovery Timing
RD, WR
tRV
MSM82C54-2RS/GS/JS
Clock & Gate Timing
WR
CLK
GATE
OUT
Mode
Count
tPWH
tWC
tCLK
tf
tPWL
tr
tWG
tWO
tGS
tGL
tGH tODG
tGS
tGW tGH
tOD
Counter
Latch
tCL
6/23
6 Page ¡ Semiconductor
MSM82C54-2RS/GS/JS
Mode definition
Mode 0
• Application: Event counter
• Output operation: The output is set to “L” level by the control word setting, and kept at “L”
level until the counter value becomes 0.
• Gate function: “H” level validates the count operation, and “L” level invalidates it. The gate
does not affect the output.
• Count value load timing: after the control word and initial count value are written, the count
value is loaded to the CE at the falling edge of the next clock pulse. The first clock pulse does
not cause the count value to be decremented. In other words, if the initial count value is N,
the output is not set to “H” level until the input of (N+1) the clock pulse after the initial count
value writing.
• Count value writing during counting:
The count value is loaded in the CE at the falling edge of the next clock, and counting with the
new count value continues. The operation for 2-byte count is as follows:
1) The counting operation is suspended when the first byte is written. The output is
immediately set to “L” level. (no clock pulse is required.)
2) After the second byte is written, the new count value is loaded to the CE at the falling edge
of the next clock.
For the output to go to “H” level again, N+1 clock pulse are necessary after new count value
N is written.
• Count value writing when the gate signal is “L” level:
The count value is also loaded to the CE at the falling edge of the next clock pulse in this case.
When the gate signal is set to “H” level, the output is set to “H” level after the lapse of N clock
pulses. Since the count value is already loaded in the CE, no clock pulse for loading in the CE
is necessary.
Mode 1
• Application: Digital one-shot
• Output operation: The output is set to “H” level by the control word setting. It is set to “L”
level at the falling edge of the clock succeeding the gate trigger, and kept at “L” level until the
counter value becomes 0. Once the output is set to “H” level, it is kept at “H” level until the
clock pulse succeeding the next trigger pulse.
• Count value load timing:
After the control word and initial count value are written, the count value is loaded to the CE
at the falling edge of the clock pulse succeeding the gate trigger and set the output to “L” level.
The one-shot pulse starts in this way. If the initial count value is N, the one-shot pulse interval
equals N clock pulses. The one-shot pulse is not repetitive.
• Gate function: The gate signal setting to “L” level after the gate trigger does not affect the
output. When it is set to “H” level again from “L” level, gate retriggering occurs, the CR count
value is loaded again, and counting continues.
• Count value writing during counting
It does not affect the one-shot pulse being counted until retriggering occurs.
12/23
12 Page | ||
Seiten | Gesamt 23 Seiten | |
PDF Download | [ M82C54-2 Schematic.PDF ] |
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